LSI LSI53C1000, Technical Manual

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SCSI Registers 4-73
SEL Selected 5
This bit is set when the LSI53C1000 is selected by
another SCSI device. For the LSI53C1000 to respond to
selection attempts, the Enable Response to Selection bit
must be set in the
SCSI Chip ID (SCID) register. The
Response ID Zero (RESPID0) and Response ID One
(RESPID1) registers must hold the chip’s ID.
RSL Reselected 4
This bit is set when the LSI53C1000 is reselected by
another SCSI device. The Enable Response to
Reselection bit must be set in the
SCSI Chip ID (SCID)
register (and the Response ID Zero (RESPID0) and
Response ID One (RESPID1) registers must hold the
chip’s ID) for the LSI53C1000 to respond to reselection
attempts.
SGE SCSI Gross Error 3
This bit is set when the LSI53C1000 encounters a SCSI
Gross Error condition. The following conditions can result
in a SCSI Gross Error:
•
Offset Underflow occurs in target mode when a
SACK/ signal is received before the corresponding
SREQ/ signal has been sent.
•
Offset Overflow occurs in initiator mode when an
SREQ/ signal is received and causes the maximum
offset, as defined by the MO[5:0] bits in the SXFER
register, to be exceeded.
•
In initiator mode, a phase change occurs with an
outstanding SREQ/SACK offset.
•
Residual Data in SCSI FIFO occurs when a transfer
other than Synchronous Data Received is started with
data left in the SCSI Synchronous Receive FIFO.
•
Multiple CRC Requests occur when, during a
synchronous DT transfer, multiple CRC requests are
received within the same offset.
•
A request for a Pad CRC word is received without the
subsequent CRC word requests.
•
A phase change occurs without a CRC Request.
Note: Checking for this condition can be disabled by setting the
DCRC bit in the CRCCNTL0 register.