LSI LSI53C1000, Technical Manual, Page: 142 / 384

4-32 Registers
EWS Enable Wide SCSI 3
When this bit is cleared, all information transfer phases
are assumed to be eight bits, transmitted on SD[7:0]/ and
SDP0/. When this bit is asserted, data transfers are
performed 16 bits at a time; the least significant byte is
on SD[7:0]/ and SDP0/, and the most significant byte is
on SD[15:8]/ and SDP1/. Command, Status, and
Message phases are not affected by this bit. Because
Ultra160 DT SCSI transfers are always wide, this bit must
be set. If it is not set, a SGE interrupt will occur.
R Reserved [2:0]
Register: 0x04
SCSI Chip ID (SCID)
Read/Write
R Reserved 7
RRE Enable Response to Reselection 6
When this bit is set, the LSI53C1000 is enabled to
respond to bus-initiated reselection at the chip ID in the
Response ID Zero (RESPID0) and Response ID One
(RESPID1) registers. Note that the chip does not
automatically reconfigure itself to the initiator mode as a
result of being reselected.
SRE Enable Response to Selection 5
When this bit is set, the LSI53C1000 is able to respond
to bus-initiated selection at the chip ID in the
Response
ID Zero (RESPID0) and Response ID One (RESPID1)
registers. Note that the chip does not automatically
reconfigure itself to target mode as a result of being
selected.
R Reserved 4
ENC[3:0] Encoded Chip SCSI ID [3:0]
These bits are used to store the LSI53C1000 encoded
SCSI ID. This is the ID which the chip asserts when
7 6 5 4 3 0
R RRE SRE R ENC[3:0]
x 0 0 x 0 0 0 0