LSI LSI53C1000, Technical Manual

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4-4 Registers
R Reserved 5
WIE Write and Invalidate Enable 4
When this bit is set, the LSI53C1000 can generate write
and invalidate commands on the PCI bus. The WRIE bit
in the
Chip Test Three (CTEST3) register must also be
set for the device to generate write and invalidate
commands.
R Reserved 3
EBM Enable Bus Mastering 2
This bit controls the ability of the LSI53C1000 to act as a
master on the PCI bus. A value of zero disables this
device from generating PCI bus master accesses. A
value of one allows the LSI53C1000 to behave as a bus
master. The device must be a bus master to fetch
SCRIPTS instructions and transfer data.
EMS Enable Memory Space 1
This bit controls the ability of the LSI53C1000 to respond
to Memory space accesses. A value of zero disables the
device response. A value of one allows the LSI53C1000
to respond to Memory Space accesses at the address
range specified by the
Base Address Register One
(BAR1) (MEMORY) , Base Address Register Two (BAR2)
(MEMORY) , Base Address Register Three (BAR3)
(SCRIPTS RAM) , and the Base Address Register Four
(BAR4) (SCRIPTS RAM) registers in the PCI
configuration space.
EIS Enable I/O Space 0
This bit controls the LSI53C1000 response to I/O space
accesses. A value of zero disables the device response.
A value of one allows the LSI53C1000 to respond to I/O
Space accesses at the address range specified by the
Base Address Register Zero (BAR0) (I/O) register in the
PCI configuration space.