LSI LSI53C1000, Technical Manual

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SCSI Registers 4-55
Register: 0x20
Reserved
This register is reserved.
Register: 0x21
Chip Test Four (CTEST4)
Read/Write
R Reserved 7
FBL3 FIFO Byte Control 3 6
This bit is used with FBL[2:0]. See Bits [2:0] description
in this register.
R Reserved [5:4]
MPEE Master Parity Error Enable 3
Setting this bit enables parity checking during master
data phases. A parity error during a bus master read is
detected by the LSI53C1000. A parity error during a bus
master write is detected by the target, and the
LSI53C1000 is informed of the error by the PERR/ pin
being asserted by the target. When this bit is cleared, the
LSI53C1000 does not interrupt if a master parity error
occurs. This bit is cleared at power-up.
FBL[2:0] FIFO Byte Control [2:0]
7 0
R
x x x x x x x x
7 6 5 4 3 2 0
R FBL3 R MPEE FBL[2:0]
0 0 0 0 0 0 0 0
FBL3 FBL2 FBL1 FBL0
DMA FIFO
Byte Lane
Pins
0 X X X Disabled N/A
1 0 0 0 0 D[7:0]
1 0 0 1 1 D[15:8]
1 0 1 0 2 D[23:16]
1 0 1 1 3 D[31:24]