LSI LSI53C1000, Technical Manual

Page: 141 / 384

SCSI Registers 4-31
WSR Wide SCSI Receive 0
When read, this bit returns the value of the Wide SCSI
Receive (WSR) flag. Setting this bit clears the WSR flag.
This bit is self-clearing.
For more information refer to Section 2.2.18, “Chained
Block Moves.”
Register: 0x03
SCSI Control Three (SCNTL3)
Read/Write
This register is automatically loaded when a Table Indirect Select or
Reselect SCRIPTS instruction is executed.
R Reserved 7
SCF[2:0] Synchronous Clock Conversion Factor [6:4]
These bits select a factor by which the frequency of
SCLK is divided before being presented to the
synchronous SCSI control logic. The synchronous
transfer speed is determined by the combination of the
divided clock and the setting of the XCLKS and XCLKH
bits in the
SCSI Control Four (SCNTL4) register. The
table below shows the clock dividers that are available.
See the table in the
SCSI Control Four (SCNTL4) register
description for a full list of available transfer rates.
7 6 4 3 2 0
R SCF[2:0] EWS R
0 0 0 0 0 0 0 0
SCF2 SCF1 SCF0
Factor
Frequency
0 0 0 SCLK/3
0 0 1 SCLK/1
0 1 0 SCLK/1.5
0 1 1 SCLK/2
1 0 0 SCLK/3
1 0 1 SCLK/4
1 1 0 SCLK/6
1 1 1 SCLK/8