LSI LSI53C1000, Technical Manual

Page: 232 / 384

4-122 Registers
Registers: 0xA0–0xA3
Shadowed Memory Move Read Selector (MMRS)
Read/Write
MMRS Shadowed Memory Move Read Selector [31:0]
When the PCI Configuration Info Enable bit in the Chip
Test Two (CTEST2) register is set, the MMRS register is
placed in the shadow mode. In this mode, the Memory
Move Read Selector (MMRS) register returns bits [31:0]
of the memory mapped operating register, PCI Base
Address Register Two (BAR2) (MEMORY) , when read.
Writes to the MMRS register have no effect. Clearing the
PCI Configuration Info Enable bit causes the MMRS
register to return to normal operation.
Registers: 0xA4–0xA7
Shadowed Memory Move Write Selector (MMWS)
Read/Write
MMWS Shadowed Memory Move Write Selector [31:0]
When the PCI Configuration Info Enable bit in the Chip
Test Two (CTEST2) register is set, the MMWS register is
placed in the shadow mode. In this mode, the MMWS
register returns bits [31:0] of the SCRIPT RAM PCI
Base
Address Register Four (BAR4) (SCRIPTS RAM) in
bits [31:0] of the MMWS register when read. Writes to the
MMWS register have no effect. Clearing the PCI
Configuration Info Enable bit causes the MMWS register
to return to normal operation.
31 0
MMRS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31 0
MMWS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0