LSI LSI53C1000, Technical Manual

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2-12 Functional Description
2.1.3.1 Enabling Cache Mode
To enable the cache logic to issue PCI cache commands (Memory Read
Line, Memory Read Multiple, and Memory Write and Invalidate) on any
PCI master operation, the following conditions must be met:
•
The Cache Line Size Enable bit in the DMA Control (DCNTL) register
must be set.
•
The PCI Cache Line Size (CLS) register must contain a valid binary
cache size, i.e., 8, 16, 32, 64, or 128 Dwords. These values are the
only valid cache sizes.
•
The programmed burst size (in Dwords) must be equal to or greater
than the cache line size register. The
DMA Mode (DMODE) register,
bits [7:6], and the Chip Test Five (CTEST5) register, bit 2, denote the
burst length.
•
The device must be performing a PCI Master transfer. The following
PCI Master transactions do not utilize the PCI cache logic, so no PCI
cache commands are issued during these types of cycles: a
nonprefetch SCRIPTS fetch, a Load/Store data transfer, and a data
flush operation. All other types of PCI Master transactions utilize the
PCI cache logic.
Not only must the above four conditions be met in order for the cache
logic to control the type of PCI cache command that is issued, proper
alignment is also necessary during write operations. If these conditions
are not met for any given PCI Master transaction, a Memory Read or
Memory Write is issued and no cache write alignment is done.
2.1.3.2 Issuing Cache Commands
In order to issue each type of PCI cache command, the corresponding
enable bit(s) must be set.
•
To issue Memory Read Line commands, the Enable Read Line
(ERL) bit in the
DMA Mode (DMODE) register must be set.
•
To issue Memory Read Multiples, the Enable Read Multiple (ERMP)
bit in the
DMA Mode (DMODE) register must be set.
•
To issue Memory Write and Invalidates, both the Write and Invalidate
Enable (WRIE) bit in the
Chip Test Three (CTEST3) register and the
Write and Invalidate Enable (WIE) bit in the PCI configuration
Command register must be set.