LSI LSI53C1000, Technical Manual

Page: 210 / 384

4-100 Registers
both ST and DT transfers as it affects data hold to the ST
edge. Setting this bit reduces the synchronous send
transfer rate but does not reduce the transfer rate at
which the LSI53C1000 can receive inbound REQs, ACKs
or data. Refer to
Table 4.4 and Table 4.5 for a summary
of available transfer rates and to Figure 4.1 through
Figure 4.3 for examples of how the XCLKH bits function.
Note: This bit does not affect CRC timings.
XCLKS_DT Extra Clock of Data Setup on DT Transfer Edge 1
Setting this bit adds a clock of data setup to synchronous
DT SCSI transfers on the DT edge. This bit only impacts
DT transfers as it only affects data setup to the DT edge.
Setting this bit reduces the synchronous transfer send
rate but does not reduce the transfer rate at which the
LSI53C1000 can receive inbound REQs, ACKs or data.
Refer to
Table 4.4 and Table 4.5 for a summary of
available transfer rates and to Figure 4.1 through
Figure 4.3 for examples of how the XCLKS bits function.
Note: This bit does not affect CRC timings.
XCLKS_ST Extra Clock of Data Setup on ST Transfer Edge 0
Setting this bit adds a clock of data setup to synchronous
DT or ST SCSI transfers on the ST edge. This bit impacts
both ST and DT transfers as it affects data setup to the
ST edge. Setting this bit reduces the synchronous send
transfer rate but does not reduce the transfer rate at
which the LSI53C1000 can receive inbound REQs, ACKs
or data. Refer to
Table 4.4 and Table 4.5 for a summary
of available transfer rates and to Figure 4.1 through
Figure 4.3 for examples of how the XCLKS bits function.
Note: This bit does not affect CRC timings.
Synchronous Receive Rate Calculation
The synchronous receive rate, in megatransfers/s, can be
calculated using the following formula:
Receive Rate (DT)
Input Clock Rate
SCF Divisor 2
×
-------------------------------------------- =
Receive Rate (ST)
Input Clock Rate
SCF Divisor 4
×
-------------------------------------------- =