LSI LSI53C1000, Technical Manual

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2-10 Functional Description
bit 2 of the Chip Test Five (CTEST5) register. If multiple cache line size
transfers are not desired, set the DMODE burst size to exactly the cache
line size and the chip will only issue single cache line transfers.
After each data transfer, the chip re-evaluates the burst size based on
the amount of remaining data to transfer. It again selects the highest
possible multiple of the cache line size, and no larger than the
DMA
Mode (DMODE) burst size. Usually, the chip selects the DMODE burst
size after alignment and issues bursts of this size. The burst size is, in
effect, throttled down toward the end of a long Memory Move or Block
Move transfer until only the cache line size left is burst size. The chip
finishes the transfer with this burst size.
Latency – In accordance with the PCI specification, the latency timer is
ignored when issuing a Memory Write and Invalidate command.
Therefore, when a latency time-out occurs, the LSI53C1000 continues to
transfer up to a cache line boundary. At that point, the chip relinquishes
the bus, and finishes the transfer at a later time using another bus
ownership. If the chip is transferring multiple cache lines it continues to
transfer until the next cache boundary is reached.
PCI Target Retry – A retry is defined as a STOP with no TRDY/,
indicating that no data was transferred. If the target issues a retry during
a Memory Write and Invalidate transfer, the chip relinquishes the bus and
immediately tries to finish the transfer on another bus ownership. The
chip issues another Memory Write and Invalidate command on the next
ownership, in accordance with the PCI specification.
PCI Target Disconnect – If the target device issues a disconnect during
a Memory Write and Invalidate transfer, the LSI53C1000 relinquishes the
bus and immediately tries to finish the transfer on another bus ownership.
The chip does not issue another Memory Write and Invalidate command
on the next ownership unless the address is aligned.
2.1.3 PCI Cache Mode
The LSI53C1000 supports the PCI specification for an 8-bit Cache Line
Size (CLS) register located in the PCI configuration space. The Cache
Line Size (CLS) register provides the ability to sense and react to
nonaligned addresses corresponding to cache line boundaries. In
conjunction with the
Cache Line Size (CLS) register, the PCI commands