SCSI Functional Description
2-25
Note:
For DT mode or when the Protocol Options field is nonzero,
the Transfer Width Exponent must be one indicating a SCSI
width of 16 bits.
Note:
The Table Indirect data (used during selection/reselection)
must be updated to enable certain control bits in the
SCNTL4 register. Specific bits to look at include: bit 7,
U3EN (Ultra160 Transfer Enable); bit 6, AIPEN
(Asynchronous Information Protection Enable); and
bits [3:0] (Extra Clock Setup/Hold).
Protocol Options (Byte 7) – A bus or device reset, power cycle, or
change between LVD/SE modes invalidates these settings. A
renegotiation resets the Protocol Options.
2.2.5.3 Asynchronous Information Protection (AIP)
The AIP feature provides error checking for asynchronous, nondata
phases through BCH encoding. During the command, status, message
in/out phases, the BCH code is transferred on the upper SCSI data bus.
For details on the BCH code, see T10 119 document "Protection for the
Asynchronous Phases".
QAS_REQ
DT_REQ
IU_REQ
Description
0
0
0
Use ST Data-In and ST Data-Out phase
to transfer data
0
1
0
Use DT Data-In and DT Data-Out phase
to transfer data with CRC
0
1
1
Use DT Data-In and DT Data-Out phase
to transfer data with information units
1
1
0
Use DT Data-In and DT Data-Out phase
to transfer data with CRC and use the
QAS method for arbitration
1
1
1
Use DT Data-In and DT Data-Out phase
to transfer data with information units and
use the QAS method for arbitration
Summary of Contents for LSI53C1000
Page 6: ...vi Preface...
Page 16: ...xvi Contents...
Page 28: ...1 12 Introduction...
Page 234: ...4 124 Registers...
Page 314: ...6 40 Specifications This page intentionally left blank...
Page 318: ...6 44 Specifications This page intentionally left blank...
Page 344: ...6 70 Specifications This page intentionally left blank...
Page 350: ...6 76 Specifications Figure 6 42 LSI53C1000 329 Ball Grid Array Bottom view...
Page 352: ...6 78 Specifications...
Page 360: ...A 8 Register Summary...
Page 376: ...IX 12 Index...