Transfer Control Instructions
5-33
DC
Data Compare Value
[7:0]
This 8-bit field is the data compared against the
register. These bits are used
in conjunction with the Data Compare Mask Field to test
for a particular data value. If the COM bit (
, bit 0) is cleared, the value in the SFBR register
may not be stable. In this case, do not use instructions
using this data compare value.
5.5.2 Second Dword
This section describes the second Dword of the Transfer Control
Instruction register.
Figure 5.10 Transfer Control Instructions - Second Dword
Jump Address
[31:0]
This 32-bit field contains the address of the next
instruction to fetch when a jump is taken. Once the
LSI53C1000 fetches the instruction from the address
pointed to by these 32-bits, this address is incremented
by 4, loaded into the
register and becomes the current instruction pointer.
5.5.3 Third Dword
This section describes the third Dword of the Transfer Control Instruction
register.
Figure 5.11 Transfer Control Instructions - Third Dword
JUMP64 Address
[31:0]
This 32-bit field contains the upper Dword of a 64-bit
address of the next instruction to fetch when a JUMP64
is taken.
31
24 23
16 15
8
7
0
DSPS Register
31
24 23
16 15
8
7
0
SFS Register (Used for JUMP64 Instruction)
Summary of Contents for LSI53C1000
Page 6: ...vi Preface...
Page 16: ...xvi Contents...
Page 28: ...1 12 Introduction...
Page 234: ...4 124 Registers...
Page 314: ...6 40 Specifications This page intentionally left blank...
Page 318: ...6 44 Specifications This page intentionally left blank...
Page 344: ...6 70 Specifications This page intentionally left blank...
Page 350: ...6 76 Specifications Figure 6 42 LSI53C1000 329 Ball Grid Array Bottom view...
Page 352: ...6 78 Specifications...
Page 360: ...A 8 Register Summary...
Page 376: ...IX 12 Index...