LSI LSI53C1000, Technical Manual

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4-94 Registers
DSKEW[1:0] Setup Data Skew Control [3:2]
These bits control the amount of skew between the SCSI
REQ/ACK signal and the SCSI data signals during setup.
The skew is affected only if the ENDSKEW bit is set.
Note: These bits are used for Ultra160 SCSI Domain Validation
only and should not be set during normal data transfer
operations.
LVDDL[1:0] LVD Drive Strength Select [1:0]
These bits control the drive level of the LVD pad drivers.
Note: This feature is for Ultra160 SCSI Domain Validation testing
environments only and should not be set during normal
data transfer operations.
The table below shows the relative strength increase or
decrease based on the LVDDL values.
Registers: 0x5C–0x5F
Scratch Register B (SCRATCHB)
Read/Write
SCRATCHB Scratch Register B [31:0]
This is a general purpose user definable scratch pad
register. Apart from CPU access, only register
Read/Write and Memory Moves directed at the
SCRATCH register will alter its contents. The power-up
values are indeterminate. A special mode of this register
can be enabled by setting the PCI Configuration Info
Enable bit in the
Chip Test Two (CTEST2) register. If this
bit is set, bits [31:13] of the Scratch Register B
(SCRATCHB) register return bits [31:13] of the PCI Base
Address Register Three (BAR3) (SCRIPTS RAM) . In this
LVDDL Drive Level
00 Nominal
01
−
20% Nominal
10 +20% Nominal
11 Reserved
31 0
SCRATCHB
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0