LSI LSI53C1000, Technical Manual

Page: 162 / 384

4-52 Registers
Register: 0x1A
Chip Test Two (CTEST2)
Read Only (bit 3 write)
R Reserved 7
SIGP Signal Process 6
This bit is a copy of the SIGP bit in the Interrupt Status
Zero (ISTAT0) register (bit 5). The SIGP bit is used to
signal a running SCRIPTS instruction. When this register
is read, the SIGP bit in the ISTAT0 register is cleared.
CIO Configured as I/O 5
This bit is defined as the Configuration I/O Enable Status
bit. This read only bit indicates if the chip is currently
enabled as I/O space.
CM Configured as Memory 4
This bit is defined as the configuration memory enable
status bit. This read only bit indicates if the chip is
currently enabled as memory space.
Note: Bits 4 and 5 may be set if the chip is mapped in both I/O
and memory space. Also, bits 4 and 5 may be set if the
chip is dual-mapped.
PCICIE PCI Configuration Info Enable 3
This bit controls the shadowing of the PCI Base Address
Register One (BAR1) (MEMORY) , PCI Base Address
Register Two (BAR2) (MEMORY) , PCI Base Address
Register Three (BAR3) (SCRIPTS RAM) , PCI Base
Address Register Four (BAR4) (SCRIPTS RAM) , PCI
Device ID , and PCI Revision ID (RID) into the Scratch
Register A (SCRATCHA) , Memory Move Read Selector
(MMRS) , Scratch Register B (SCRATCHB) , Memory
Move Write Selector (MMWS) , and SCRIPT Fetch Selec-
tor (SFS) registers.
When it is set, MMWS contains bits [63:32] and
SCRATCH B contains bits [31:0] of the RAM Base
Address value from the PCI Configuration
Base Address
7 6 5 4 3 2 0
R SIGP CIO CM PCICIE R
x 0 x x 0 x x x