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PCI Functional Description

2-11

Memory Read Line (MRL), Memory Read Multiple (MRM), and Memory
Write and Invalidate (MWI) are individually software enabled or disabled.

Table 2.2

provides information on the PCI cache mode alignment.

Table 2.2

PCI Cache Mode Alignment

Host Memory

0x00

0x04

0x08

0x0C

0x10

0x14

0x18

0x1C

0x20

0x24

0x28

0x2C

0x30

0x34

0x38

0x3C

0x40

0x44

0x48

0x4C

0x50

0x54

0x58

0x5C

0x60

Summary of Contents for LSI53C1000

Page 1: ...S14050 A LSI53C1000 PCI to Ultra160 SCSI Controller TECHNICAL MANUAL F e b r u a r y 2 0 0 1 Version 2 1...

Page 2: ...at any time without notice LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein except as expressly agreed to in writing by L...

Page 3: ...owing chapters and appendixes Chapter 1 Introduction describes the general information about the LSI53C1000 Chapter 2 Functional Description describes the main functional areas of the chip in greater...

Page 4: ...CO 80112 800 854 7179 or 303 397 7956 outside U S FAX 303 397 2740 Ask for document number X3 131 1994 SCSI 2 or X3 253 SCSI 3 Parallel Interface ENDL Publications 14426 Black Walnut Court Saratoga C...

Page 5: ...he word deassert means to drive a signal false or inactive Hexadecimal numbers are indicated by the prefix 0x for example 0x32CF Binary numbers are indicated by the prefix 0b for example 0b0011 0010 1...

Page 6: ...vi Preface...

Page 7: ...n 1 9 1 6 4 Ease of Use 1 10 1 6 5 Flexibility 1 10 1 6 6 Reliability 1 11 1 6 7 Testability 1 11 Chapter 2 Functional Description 2 1 PCI Functional Description 2 3 2 1 1 PCI Addressing 2 3 2 1 2 PCI...

Page 8: ...d Mode 2 62 2 5 Power Management 2 62 2 5 1 Power State D0 2 63 2 5 2 Power State D1 2 63 2 5 3 Power State D2 2 64 2 5 4 Power State D3 2 64 Chapter 3 Signal Descriptions 3 1 Signal Organization 3 1...

Page 9: ...e Instructions 5 23 5 4 1 First Dword 5 23 5 4 2 Second Dword 5 24 5 4 3 Read Modify Write Cycles 5 24 5 4 4 Move To From SFBR Cycles 5 25 5 5 Transfer Control Instructions 5 27 5 5 1 First Dword 5 27...

Page 10: ...rface SCSI Data Paths 2 37 2 4 Regulated Termination for Ultra160 SCSI 2 40 2 5 Determining the Synchronous Transfer Rate 2 45 2 6 Interrupt Routing Hardware Using the LSI53C1000 2 54 2 7 Chained Bloc...

Page 11: ...10 6 8 External Clock 6 11 6 9 Reset Input 6 12 6 10 Interrupt Output 6 13 6 11 PCI Configuration Register Read 6 15 6 12 PCI Configuration Register Write 6 16 6 13 Operating Registers SCRIPTS RAM Re...

Page 12: ...ous Transfer 6 69 6 41 LSI53C1000 329 BGA Chip Top View 6 72 6 42 LSI53C1000 329 Ball Grid Array Bottom view 6 76 6 43 LSI53C1000 329 BGA Mechanical Drawing 6 77 B 1 16 Kbyte Interface with 200 ns Mem...

Page 13: ...Transfer Rates 4 105 4 5 Single Transition Transfer Rates 4 106 5 1 Read Write Instructions 5 25 6 1 Absolute Maximum Stress Ratings 6 2 6 2 Operating Conditions 6 2 6 3 LVD Driver SCSI Signals SD 15...

Page 14: ...d Data 6 24 6 24 Burst Opcode Fetch 32 Bit Address and Data 6 26 6 25 Back to Back Read 32 Bit Address and Data 6 28 6 26 Back to Back Write 32 Bit Address and Data 6 30 6 27 Burst Read 32 Bit Address...

Page 15: ...6 6 47 SCSI 2 Fast Transfers 10 0 Mbytes 8 Bit Transfers or 20 0 Mbytes 16 Bit Transfers 40 MHz Clock 6 67 6 48 Ultra SCSI SE Transfers 20 0 Mbytes 8 Bit Transfers or 40 0 Mbytes 16 Bit Transfers Quad...

Page 16: ...xvi Contents...

Page 17: ...station and server designs making it easy to add a high performance SCSI bus to any PCI system The LSI53C1000 supports a 64 bit or 32 bit 66 or 33 MHz PCI bus The Ultra160 SCSI features implemented in...

Page 18: ...of Low Voltage Differential LVD LVDlink transceivers allow the LSI53C1000 to perform either Single Ended SE or LVD transfers The LSI53C1000 integrates a high performance SCSI core a 64 bit 66 MHz PCI...

Page 19: ...ing is a list of LSI53C1000 features Supports 66 MHz PCI Complies with PCI 2 2 specification Supports Ultra160 DT clocking for data transfers up to 160 Mbytes s Fixed Disk Optical Disk Printer Tape an...

Page 20: ...fers s resulting in approximately double the synchronous data transfer rates of Ultra2 SCSI The LSI53C1000 performs 16 bit Ultra160 SCSI synchronous data transfers as fast as 160 Mbytes s This advanta...

Page 21: ...nterconnect management solution It ensures robust and low risk Ultra160 SCSI implementations by extending the Domain Validation guidelines documented in the ANSI T10 SPI 3 specifications Domain Valida...

Page 22: ...vides a long term migration path to even faster SCSI transfer rates without compromising signal integrity cable length or connectivity For backward compatibility to existing SE devices the LSI53C1000...

Page 23: ...liability in real world cabling environments TolerANT technology is compatible with both the Alternative One and Alternative Two termination schemes proposed by the American National Standards Institu...

Page 24: ...r gather data transfers Performs sustained Memory to Memory DMA transfers to approximately 100 Mbytes s Minimizes the SCSI I O start latency Performs complex bus sequences without interrupts including...

Page 25: ...es up to 8 Dwords of SCRIPTS instructions Bursts SCRIPTS opcode fetches across the PCI bus Performs zero wait state bus master data bursts up to 528 Mbytes s 66 MHz Supports PCI Cache Line Size CLS re...

Page 26: ...General Purpose Software for PC based operating system support Support for relative jumps SCSI Selected As ID bits for responding with multiple IDs 1 6 5 Flexibility The following features increase th...

Page 27: ...CC certification Latch up protection greater than 150 mA Voltage feed through protection minimum leakage current through SCSI pads A high proportion of pins are power and ground Power and ground isola...

Page 28: ...1 12 Introduction...

Page 29: ...tion 2 1 PCI Functional Description Section 2 2 SCSI Functional Description Section 2 3 Parallel ROM Interface Section 2 4 Serial EEPROM Interface Section 2 5 Power Management The LSI53C1000 is compos...

Page 30: ...S RAM 8 Dword SCRIPTS Prefetch Buffer Operating Registers SCSI SCRIPTS Processor 944 Byte DMA FIFO SCSI FIFO and SCSI Control Block Universal TolerANT Drivers and Receivers 64 Bit PCI Interface PCI Co...

Page 31: ...space The IDSEL bus signal is a chip select that allows access to the configuration register space only A configuration read write cycle without IDSEL is ignored The host processor uses the eight lowe...

Page 32: ...on uses an 8 Kbyte SCRIPTS RAM memory space Base Address Register Two BAR2 MEMORY determines the 8 Kbyte memory area the SCRIPTS RAM occupies 2 1 2 PCI Bus Commands and Functions Supported Bus command...

Page 33: ...upper 32 address bits 2 1 2 4 I O Write Command The LSI53C1000 uses the I O Write command to write data to an agent mapped in the I O address space When decoding I O cycles the LSI53C1000 decodes the...

Page 34: ...00 by asserting its IDSEL signal when AD 1 0 are 0b00 During the address phase of a configuration cycle AD 7 2 address one of the 64 Dword registers in the configuration space of each device C_BE 3 0...

Page 35: ...ze CLS register contains a legal burst size value 8 16 32 64 or 128 Dwords that is less than or equal to the DMODE burst size The transfer crosses a cache line boundary When these conditions are met t...

Page 36: ...opcode fetches when the following conditions are met The CLSE bit Cache Line Size Enable bit 7 of the DMA Control DCNTL register is set The ERL bit Enable Read Line bit 3 of the DMA Mode DMODE regist...

Page 37: ...Chip Test Three CTEST3 register Bit 4 of the PCI Configuration Command register The Cache Line Size CLS register contains a legal burst size value 8 16 32 64 or 128 Dwords that is less than or equal...

Page 38: ...the transfer at a later time using another bus ownership If the chip is transferring multiple cache lines it continues to transfer until the next cache boundary is reached PCI Target Retry A retry is...

Page 39: ...date MWI are individually software enabled or disabled Table 2 2 provides information on the PCI cache mode alignment Table 2 2 PCI Cache Mode Alignment Host Memory A 0x00 B 0x04 0x08 C 0x0C D 0x10 0x...

Page 40: ...cycles a nonprefetch SCRIPTS fetch a Load Store data transfer and a data flush operation All other types of PCI Master transactions utilize the PCI cache logic Not only must the above four conditions...

Page 41: ...r are read in one PCI burst transaction If the transfer crosses a Dword boundary A 1 0 0b00 a Memory Read Line command is issued If the transfer crosses a cache boundary as specified by the cache line...

Page 42: ...Memory Write and Invalidate Read Example 1 Burst 4 Dwords Cache Line Size 4 Dwords A to B MRL 6 bytes A to C MRL 13 bytes A to D MRM 16 bytes MR 1 byte C to D MRM 5 bytes C to E MRM 16 bytes MRM 5 by...

Page 43: ...C MRL 13 bytes A to D MRM 17 bytes C to D MRM 5 bytes C to E MRM 21 bytes D to F MRM 32 bytes A to H MRM 32 bytes MRM 32 bytes MRM 17 bytes A to G MRM 32 bytes MRM 32 bytes MR 2 bytes A to B MRL 6 by...

Page 44: ...bytes A to C MW 13 bytes A to D MW 17 bytes C to D MW 5 bytes C to E MW 3 bytes MWI 16 bytes MW 2 bytes D to F MW 15 bytes MWI 16 bytes MW 1 byte A to H MW 15 bytes MWI 16 bytes MWI 16 bytes MWI 16 by...

Page 45: ...MW 5 bytes C to E MW 3 bytes MWI 16 bytes MW 2 bytes D to F MW 15 bytes MWI 16 bytes MW 1 byte A to H MW 15 bytes MWI 32 bytes MWI 32 bytes MW 2 bytes A to G MW 15 bytes MWI 32 bytes MWI 16 bytes MW...

Page 46: ...The LSI53C1000 can be programmed with SCSI SCRIPTS making it easy to fine tune the system for specific mass storage devices or Ultra160 SCSI requirements Figure 2 1 on page 2 2 illustrates the relati...

Page 47: ...ely eliminate the need for CPU intervention during an I O disconnect reselect sequence SCRIPTS control the storage of appropriate information needed to restart the I O state eliminating the need for p...

Page 48: ...n space contain the base address of the internal RAM To simplify SCRIPTS instruction loading the base address of the RAM appears in the Scratch Register B SCRATCHB register when bit 3 of the Chip Test...

Page 49: ...any one SCRIPTS operation is not permitted Therefore software must handle all such transactions 2 2 4 Hardware Control of SCSI Activity LED The LSI53C1000 controls an LED through the GPIO_0 pin to ind...

Page 50: ...refer to the SCSI Parallel Interface 3 SPI 3 working document that is available on the world wide web at the T10 Home Page http www t10 org Also check the SCSI Trade Association web site at http www...

Page 51: ...valid using a LVD SCSI bus In order to support DT clocking there are two new phases for the SCSI bus The old Data In and Data Out phases are now called ST Data In and ST Data Out The new phases are D...

Page 52: ...an a clock period of 50 ns but a data rate of 40 megatransfers s 25 ns In ST mode 0x0A would mean a clock period of 25 ns and a data rate of 40 megatransfers s Req Ack Offset Byte 5 Req Ack Offset is...

Page 53: ...Options 2 2 5 3 Asynchronous Information Protection AIP The AIP feature provides error checking for asynchronous nondata phases through BCH encoding During the command status message in out phases the...

Page 54: ...t in the AIP Control Zero AIPCNTL0 register indicates if the error is an AIP error 2 2 5 4 Register Considerations The following is a summary of the registers and bits required to enable Ultra160 SCSI...

Page 55: ...parity CRC AIP error while receiving or sending SCSI data For more information see SCSI Control One SCNTL1 bit 5 The Chip Control Three CCNTL3 register Bit 4 ENDSKEW Enable REQ ACK to Data skew contr...

Page 56: ...ers as it affects data setup to the DT edge Bit 0 XCLKS_ST Extra Clock of Data Setup on ST Transfer Edge is set to add a clock of data setup to synchronous DT or ST SCSI transfers on the ST edge This...

Page 57: ...for a CRC request prior to a phase change on the SCSI bus This condition creates a SCSI error condition and makes the device noncompliant with the SPI 3 specification Do not set these bits under norm...

Page 58: ...ring normal operation as corrupt CRC values result Bits 1 0 CRCDSEL 1 0 CRC Data Register Selector control the data visible in the CRC Data register The CRC Data CRCD register Bits 31 0 CRCDATA CRC Da...

Page 59: ...d Multiple if PCI caching is enabled Note This feature is only useful when fetching SCRIPTS instructions from main memory Due to the short access time of SCRIPTS RAM prefetching is not necessary when...

Page 60: ...truction fetches If the instruction is a Memory to Memory Move the third Dword is accessed in a separate ownership If the instruction is an indirect type the additional Dword is accessed in a subseque...

Page 61: ...TCK clock cycles The LSI53C1000 uses an 8 bit instruction register to support all boundary scan instructions The data registers included in the device are the Boundary Data register the IDCODE registe...

Page 62: ...rity CRC AIP Error Target Mode Only SCSI Control One SCNTL1 Bit 5 This bit determines if the LSI53C1000 halts operations when a parity error is detected in target mode Enable Parity CRC AIP Error Inte...

Page 63: ...eport CRC errors during Ultra160 transfers Disable CRC Protocol Checking CRC Control Zero CRCCNTL0 Bit 6 This bit is set to cause the device not to check for a CRC request prior to a phase change on t...

Page 64: ...O mode 112 bytes is not supported by the LSI53C1000 Figure 2 2 DMA FIFO Sections The LSI53C1000 supports 64 bit memory and automatically supports misaligned DMA transfers The FIFO allows the LSI53C100...

Page 65: ...ster contains the actual number of bytes remaining in the DMA FIFO In addition the SCSI Output Data Latch SODL register must be checked to determine if it contains any remaining bytes If bit 5 OLF in...

Page 66: ...ytes remaining in the DMA FIFO To recover from all other error conditions clear the DMA FIFO by setting bit 2 CLF in Chip Test Three CTEST3 and retry the I O If the Wide SCSI Send WSS bit in the SCSI...

Page 67: ...and a long term migration path for faster SCSI transfer rates HVD is not supported by this device Bit 2 of the SCSI Status Two SSTAT2 register and bit 5 of the SCSI Status Two SSTAT2 register are now...

Page 68: ...cted while trying to perform selection reselection This situation may occur when a SCSI controller operating in the initiator mode tries to select a target and is reselected by another The Select 4 5...

Page 69: ...initiator and target modes The LSI53C1000 s SCLK input must be connected to a 40 MHz oscillator The SCSI Transfer SXFER register controls the synchronous offset while the SCSI Control Three SCNTL3 reg...

Page 70: ...CSI Control Four SCNTL4 register description for a full list of available synchronous transfer rates 2 2 15 2 SCSI Control Four SCNTL4 Register Bits 3 0 Description The following extra clock bits add...

Page 71: ...ta Bit 0 XCLKS_ST Extra Clock of Data Setup on ST transfer edge adds a clock of data setup to synchronous DT or ST SCSI transfers on the ST edge This bit impacts DT and ST transfers as it affects data...

Page 72: ...ng SCNTL3 and SCNTL4 program the register to 160 Mbytes s transfer rate Step 3 Program the Maximum SCSI Offset Using SXFER program the maximum SCSI DT Synchronous offset to 0x3E Step 4 Enable TolerANT...

Page 73: ...f an interrupt condition by polling or hardware interrupts Polling means that the microprocessor must continually loop and read a register until it detects a bit that is set 40 MHz Clock Quadrupler SC...

Page 74: ...ormation ISTAT The ISTAT register includes the Interrupt Status Zero ISTAT0 Interrupt Status One ISTAT1 Mailbox Zero MBOX0 and Mailbox One MBOX1 registers It is the only register that can be accessed...

Page 75: ...terrupt Enable One SIEN1 or not Reading these registers determines the conditions that caused the SCSI type interrupt clears any bits that are set in SIST0 and SIST1 and clears the SIP bit in Interrup...

Page 76: ...FIFO in CTEST3 bit SIEN0 and SIEN1 The SCSI Interrupt Enable Zero SIEN0 and SCSI Interrupt Enable One SIEN1 registers are the interrupt enable registers for the SCSI interrupts in SCSI Interrupt Statu...

Page 77: ...interrupts are not needed for events that occur during high level SCRIPTS operation 2 2 16 4 Masking Masking an interrupt means disabling or ignoring that interrupt Clearing bits in the SCSI Interrupt...

Page 78: ...in the Interrupt Status Zero ISTAT0 register are set first level then there is already at least one pending interrupt Any future interrupts are stacked in extra registers behind the SCSI Interrupt Sta...

Page 79: ...upt occurs the LSI53C1000 attempts to halt in an orderly fashion If the interrupt occurs in the middle of an instruction fetch the fetch is completed except in the case of a Bus Fault Execution does n...

Page 80: ...urred and determine what action is required to service the interrupts 5 If both the SIP and DIP bits are set read SCSI Interrupt Status Zero SIST0 SCSI Interrupt Status One SIST1 and DMA Status DSTAT...

Page 81: ...INT_DIR pin of the LSI53C1000 When a RAID upgrade card is not installed interrupts from a SCSI core must not be presented to the system s interrupt controller using multiple interrupt inputs Figure 2...

Page 82: ...ubsystem ID using a serial EPROM on power up If bit 15 in this ID is set the LSI Logic BIOS and operating system drivers will ignore the chip This makes it possible to control the assignment of the ma...

Page 83: ...CRIPTS instruction along with the Wide SCSI Send WSS and Wide SCSI Receive WSR bits in the SCSI Control Two SCNTL2 register are used to facilitate these situations The Chained Block Move instruction i...

Page 84: ...the lower byte of the SCSI Output Data Latch SODL register for asynchronous transfers or in the chain byte holding register for synchronous transfers and the WSS flag is set The hardware uses the WSS...

Page 85: ...s the high order byte of a partial SCSI transfer which has not yet been transferred to memory This stored data may be a residue byte and therefore ignored or it may be valid data that is transferred t...

Page 86: ...al transfer terminates the Chained Block Move the WSS flag is set The low order byte should be stored in the lower byte of the SCSI Output Data Latch SODL register for asynchronous transfers or in the...

Page 87: ...HC or HCT external components to be used Pull up resistors on the 8 bit bidirectional memory bus at power up determine the memory size and speed The LSI53C1000 senses this bus shortly after the releas...

Page 88: ...e the size of the available external memory using the Expansion ROM Base Address register in the PCI configuration space For more information on how this works refer to the PCI specification or the Ex...

Page 89: ...load is enabled and an EEPROM is not present or the checksum fails the Subsystem ID and Subsystem Vendor ID registers read back all zeros At power up five bytes are loaded into the chip from locations...

Page 90: ...d power state The LSI53C1000 power states are independently controlled through two power state bits that are located in the PCI Configuration Space Power Management Control Status PMCSR register 0x44...

Page 91: ...CSI CLK Therefore D2 includes this attribute as well as the attributes defined in the Power State D2 section The PCI Function Power States D0 D1 D2 and D3 are described below 2 5 1 Power State D0 Powe...

Page 92: ...re restored Also any pending interrupts before the function entered power state D2 are asserted 2 5 4 Power State D3 Power state D3 is the minimum power state which includes settings called D3hot and...

Page 93: ...on 3 5 General Purpose I O GPIO Signals Section 3 6 Flash ROM and Memory Interface Signals Section 3 7 Test Interface Signals Section 3 8 Power and Ground Signals Section 3 9 MAD Bus Programming 3 1 S...

Page 94: ...re 3 1 illustrates the signal groupings Pinout information and package drawings are available in Section 6 6 Package Drawings I Input a standard input only signal O Output a standard output driver typ...

Page 95: ...MWE MCE MOE _TESTOUT MAS0 MAS1 MAD 7 0 SCLK SD 15 0 SDP 1 0 SC_D SI_O SMSG SREQ SBSY SATN SRST SSEL TEST_RST TEST_HSC MOE _TESTOUT TCK TMS TDI TDO DIFFSENS LSI53C1000 Interface SCSI Bus Interface Syst...

Page 96: ...errupt Signals and GPIO Signals Table 3 1 LSI53C1000 Internal Pull ups and Pull downs Pin Name Pull up Current Conditions for Pull up INTA ALT_INTA 25 A Pull up enabled when the AND tree mode is enabl...

Page 97: ...A Enable66 controls the 66C bit in the PCI Configuration Space This bit indicates whether or not the chip is 66 MHz capable This pin has a static pull up M66EN B1 I N A M66EN is used to enable the 66...

Page 98: ...rite bursts AD 7 0 define the least significant byte and AD 63 56 define the most significant byte C_BE 7 0 AA4 AC3 AB4 AC4 K1 P1 T2 V3 T S 8 mA PCI Bus Command and Byte Enables are multiplexed on the...

Page 99: ...phase is completed on any clock when both TRDY and IRDY are sampled asserted During a read TRDY indicates that valid data is present on the AD bus During a write it indicates that the target is prepa...

Page 100: ...access to the PCI bus has been granted This is a point to point signal Every master has its own GNT signal Table 3 6 Error Reporting Signals Name Bump Type Strength Description PERR R4 S T S 8 mA PCI...

Page 101: ...n interrupt condition requires service from the host CPU The output drive of this pin is an open drain See SCSI Test One STEST1 bits 1 0 for additional information about disabling this interrupt in a...

Page 102: ...it SCSI data bus SD 15 0 A5 D5 A4 A3 C19 B19 C18 B18 B10 C10 B9 C9 B8 C8 B7 A6 I O SE 48 mA SCSI LVD 12 mA UniLVD SCSI Data LVD Mode Positive half of LVDlink pair for SCSI data lines SD 15 0 form the...

Page 103: ...etween 0 7 V and 1 9 V is present the SCSI bus operates in the LVD mode SE Mode When this pin is driven LOW below 0 5 V the SCSI bus operates in the SE mode HVD Mode When this pin is detected HIGH abo...

Page 104: ...SC_D SC_D SI_O SI_O SMSG SMSG SREQ SREQ SACK SACK SBSY SBSY SATN SATN SRST SRST SSEL SSEL C15 A16 B17 C17 C14 A15 C16 A17 C13 A14 C12 A12 B11 B12 B14 D13 B15 D15 I O SE 48 mA SCSI LVD 12 mA UniLVD SC...

Page 105: ...will be an opcode fetch if bit 6 in the General Purpose Pin Control GPCNTL register is set it indicates if the next bus request is an opcode fetch GPIO1_ MASTER Y16 I O 8 mA General Purpose I O pin 1...

Page 106: ...flash memory Since the LSI53C1000 moves addresses eight bits at a time this pin connects to the clock of an external bank of flip flops that assemble up to a 20 bit address for the external memory MAS...

Page 107: ...poses only Pulled HIGH internally MOE _ TESTOUT Y18 O 4 mA Memory Output Enable This pin is used as an output enable signal to an external EPROM or flash memory during read operations It is also used...

Page 108: ...ower for PCI bus drivers receivers SCSI bus drivers receivers local memory interface drivers receivers and other I O pins VDD_CORE B22 B23 D3 E4 Y13 AB3 AB18 AB23 AC1 P N A Power for core logic VSS_CO...

Page 109: ...AA14 AA15 AA23 AB15 AB22 AC15 AC16 B13 B16 B21 D16 D22 D23 E20 E21 E22 E23 F2 F20 F21 F22 F23 G3 G21 G22 G23 H20 H21 H22 H23 J20 J21 J22 J23 K21 K22 K23 L20 L21 L22 L23 M23 N20 N21 N22 N23 P21 P22 P23...

Page 110: ...r is attached while a 1 indicates a pull up resistor attached MAD 0 slow ROM When pulled up this pin enables use of slower memory devices by including two extra data access cycles Note All MAD pins ha...

Page 111: ...egisters Section 4 2 SCSI Registers Section 4 3 SCSI Shadow Registers 4 1 PCI Configuration Registers To access the PCI Configuration registers perform a configuration read or write to a device with i...

Page 112: ...1 0 0x14 4 10 Base Address Register Two BAR2 MEMORY bits 31 0 0x18 4 10 Base Address Register Three BAR3 SCRIPTS RAM bits 31 0 0x1C 4 11 Base Address Register Four BAR4 SCRIPTS RAM bits 31 0 0x20 4 11...

Page 113: ...onfiguration accesses R Reserved 15 9 SE SERR Enable 8 When this bit is set the LSI53C1000 enables the SERR driver SERR is disabled when this bit is cleared The default value of this bit is zero This...

Page 114: ...transfer data EMS Enable Memory Space 1 This bit controls the ability of the LSI53C1000 to respond to Memory space accesses A value of zero disables the device response A value of one allows the LSI53...

Page 115: ...error even if data parity error handling is disabled SSE Signaled System Error 14 This bit is set whenever the device asserts the SERR signal RMA Received Master Abort from Master 13 A master device s...

Page 116: ...r the errant operation and The Parity Error Response bit in the Command register is set FBBC Fast Back to Back Capable 7 This bit is zero R Reserved 6 66C 66 MHz Capable 5 When set this bit indicates...

Page 117: ...in units of 32 bit words The value in this register is used by the device to determine whether to use Write and Invalidate or Write commands for performing write cycles and whether to use Read Read L...

Page 118: ...owing equation to calculate an optimum latency value for the SCSI function Latency 2 Burst Size typical wait states 1 Values greater than optimum are also acceptable Register 0x0E Header Type HT Read...

Page 119: ...erating register set into I O space The LSI53C1000 requires 256 bytes of I O space for this base address register Bit 0 is hardwired to one Bit 1 is reserved and returns a zero on all reads All other...

Page 120: ...of this register refer to the PCI 2 2 specification Registers 0x18 0x1B Base Address Register Two BAR2 MEMORY Read Write BAR2 Base Address Register Two 31 0 This base address register in conjunction...

Page 121: ...he operation of this register refer to the PCI 2 2 specification Registers 0x20 0x23 Base Address Register Four BAR4 SCRIPTS RAM Read Write BAR4 Base Address Register Four 31 0 This base address regis...

Page 122: ...r subsystem where this PCI device resides It provides a mechanism for an add in card vendor to distinguish its cards from another vendor s cards even if the cards have the same PCI controller installe...

Page 123: ...0x2E 0x2F Subsystem ID SID Read Only SID Subsystem ID 15 0 This 16 bit register is used to uniquely identify the add in board or subsystem where this PCI device resides It provides a mechanism for an...

Page 124: ...s represents the binary version of the external memory size For example to indicate an external memory size of 32 Kbytes this register when written with ones and read back returns ones in the upper 17...

Page 125: ...rst extended capability register is located at offset 0x40 in PCI Configuration Space Registers 0x35 0x37 Reserved This register is reserved Registers 0x38 0x3B Reserved This register is reserved 7 0...

Page 126: ...ster tells which input of the system interrupt controller s the device s interrupt pin is connected to Values in this register are specified by system architecture Register 0x3D Interrupt Pin IP Read...

Page 127: ...5 s The LSI53C1000 sets this register to 0x11 Register 0x3F Max_Lat ML Read Only ML Max_Lat 7 0 This register is used to specify the desired settings for latency timer values Max_Lat is used to specif...

Page 128: ...the function s capabilities list The LSI53C1000 has these bits set to zero indicating no further extended capabilities registers exist Registers 0x42 0x43 Power Management Capabilities PMC Read Only...

Page 129: ...on 5 This bit is cleared to indicate that the LSI53C1000 requires no special initialization before the generic class device driver is able to use it R Reserved 4 PMEC PME Clock 3 Bit 3 is cleared beca...

Page 130: ...is disabled R Reserved 7 2 PWS 1 0 Power State 1 0 Bits 1 0 are used to determine the current power state of the LSI53C1000 They are used to place the LSI53C1000 in a new power state Power states are...

Page 131: ...ase Mismatch Jump Address Two PMJAD2 Remaining Byte Count RBC Updated Address UA Entry Storage Address ESA Instruction Address IA SCSI Byte Count SBC and the Cumulative SCSI Byte Count CSBC All the ph...

Page 132: ...SIEN1 SIEN0 0x40 4 68 GPCNTL CCNTL2 SWIDE Reserved 0x44 4 76 RESPID1 RESPID0 STIME1 STIME0 0x48 4 78 STEST3 STEST2 STEST1 STEST0 0x4C 4 81 CSO STEST4 SIDL 0x50 4 87 CCNTL1 CCNTL0 SODL 0x54 4 88 CCNTL3...

Page 133: ...Arbitration bit bit 3 in the SCSI Status Zero SSTAT0 register 3 After an arbitration delay the CPU should read the SCSI Bus Data Lines SBDL register to check if a higher priority SCSI ID is present If...

Page 134: ...lection by asserting SSEL the target s ID stored in the SCSI Destination ID SDID register and the LSI53C1000 s ID stored in the SCSI Chip ID SCID register onto the SCSI bus 6 After a selection is comp...

Page 135: ...ynchronous or ST synchronous the SCSI data bus is checked for odd parity when data is received from the SCSI bus in either the initiator or the target mode If a parity error is detected bit 0 of the S...

Page 136: ...ting SACK during the byte transfer with the parity error Also set the Enable Parity CRC AIP Checking bit for the LSI53C1000 to assert SATN in this manner A parity error or CRC error is detected on dat...

Page 137: ...g or operation in low level mode DHP Disable Halt on Parity CRC AIP Error or ATN Target Only 5 The DHP bit is only defined for the target mode When this bit is cleared the LSI53C1000 halts the SCSI da...

Page 138: ...croprocessor or a SCRIPTS loop AESP Assert Even SCSI Parity force bad parity 2 When this bit is set the LSI53C1000 asserts even parity It forces a SCSI parity error on each byte sent to the SCSI bus f...

Page 139: ...is possible to perform a low level selection instead The abort completes because the LSI53C1000 loses arbitration This is detected by the clearing of the Immediate Arbitration bit Do not use the Lost...

Page 140: ...ns the value of the Wide SCSI Send WSS flag Asserting this bit clears the WSS flag This clearing function is self clearing For more information refer to Section 2 2 18 Chained Block Moves VUE0 Vendor...

Page 141: ...or 6 4 These bits select a factor by which the frequency of SCLK is divided before being presented to the synchronous SCSI control logic The synchronous transfer speed is determined by the combination...

Page 142: ...eselection 6 When this bit is set the LSI53C1000 is enabled to respond to bus initiated reselection at the chip ID in the Response ID Zero RESPID0 and Response ID One RESPID1 registers Note that the c...

Page 143: ...et mode Table 4 3 describes the possible combinations and their relationship to the synchronous data offset used by the LSI53C1000 These bits determine the LSI53C1000 method of transfer for ST DT Data...

Page 144: ...ting SCRIPTS the SCRIPTS processor writes the destination SCSI ID to this register The SCSI ID is defined by the user in a SCRIPTS Select or Reselect instruction The value written is the binary encode...

Page 145: ...tput these pins can be used to enable or disable external terminators It is also possible to program these signals as live inputs and sense them through a SCRIPTS register to register Move Instruction...

Page 146: ...fy writes with the SCSI First Byte Received SFBR as the destination This allows bit testing after an operation The SCSI First Byte Received SFBR is not writable using the CPU and therefore not by a Me...

Page 147: ...transferring data using programmed I O Some bits are set or cleared when executing SCSI SCRIPTS Do not write to the register once the LSI53C1000 starts executing normal SCSI SCRIPTS REQ Assert SCSI RE...

Page 148: ...bits are invalid for targets that are selected under the single initiator option of the SCSI 1 specification This condition is detected by examining the VAL bit above Register 0x0B SCSI Bus Control Li...

Page 149: ...red It is possible to mask DMA interrupt conditions individually through the DMA Interrupt Enable DIEN register When performing consecutive 8 bit reads of the DMA Status DSTAT SCSI Interrupt Status Ze...

Page 150: ...register SSI Single Step Interrupt 3 If the Single Step Mode bit in the DMA Control DCNTL register is set this bit is set and an interrupt generated after successful execution of each SCRIPTS instruct...

Page 151: ...Load and Store instruction is issued when the register address is not aligned with the memory address A Load and Store instruction is issued with bit 5 in the DMA Command DCMD register cleared or bit...

Page 152: ...ata Latch SODL contains data The SODL register is the interface between the DMA logic and the SCSI bus for asynchronous send operations In the asynchronous mode data is transferred from the host bus t...

Page 153: ...e SCSI SDP0 parity signal This signal is not latched and may change as it is read Register 0x0E SCSI Status One SSTAT1 Read Only R Reserved 7 4 SDP0L Latched SCSI Parity 3 This bit reflects the SCSI p...

Page 154: ...in the SCSI Input Data Latch SIDL contains data Data is transferred from the SCSI bus to the SCSI Input Data Latch register before being sent to the DMA FIFO The data is then sent to the host bus The...

Page 155: ...ted bit in SCNTL1 is off This bit is cleared when a Block Move instruction is executed while the Connected bit in SCNTL1 is set SDP1 SCSI SDP1 Parity Signal 0 This bit represents the present state of...

Page 156: ...t any operation is 1 Set this bit 2 Wait for an interrupt 3 Read the Interrupt Status Zero ISTAT0 register 4 If the SCSI Interrupt Pending bit is set read the SCSI Interrupt Status Zero SIST0 or SCSI...

Page 157: ...ause of the jump The SIGP bit is usable at any time and is not restricted to the wait for selection reselection condition SEM Semaphore 4 The SCRIPTS processor may set this bit using a SCRIPTS registe...

Page 158: ...ed before servicing any other interrupts indicated by SIP or DIP After it has been set this bit must be written to one to clear it SIP SCSI Interrupt Pending 1 This status bit is set when an interrupt...

Page 159: ...ad Write R Reserved 7 3 FLSH Flushing 2 If this bit is set the chip is flushing data from the DMA FIFO If cleared no flushing is occurring This bit is read only Writes do not affect the value of this...

Page 160: ...r Note The host and the SCRIPTS processor code could access the same mailbox byte at the same time Using one mailbox register as read only and the other as write only prevents this conflict Register 0...

Page 161: ...ytes at the bottom of the FIFO Therefore if all FMT bits are set the DMA FIFO is empty Register 0x19 Chip Test One CTEST1 Read Only FFL Byte Full in DMA FIFO 7 0 These status bits identify the upper b...

Page 162: ...rently enabled as memory space Note Bits 4 and 5 may be set if the chip is mapped in both I O and memory space Also bits 4 and 5 may be set if the chip is dual mapped PCICIE PCI Configuration Info Ena...

Page 163: ...this bit is cleared the SCRATCH A MMRS SCRATCH B MMWS and SFS registers return to normal operation Note Bit 3 is the only writable bit in this register All other bits are read only When modifying this...

Page 164: ...on Command register must also be set for the chip to generate Write and Invalidate commands Registers 0x1C 0x1F Temporary TEMP Read Write TEMP Temporary 31 0 This 32 bit register stores the Return ins...

Page 165: ...a bus master read is detected by the LSI53C1000 A parity error during a bus master write is detected by the target and the LSI53C1000 is informed of the error by the PERR pin being asserted by the ta...

Page 166: ...ST5 Read Write ADCK Clock Address Incrementor 7 Setting this bit increments the address pointer contained in the DMA Next Address DNAD register The DNAD register is incremented based on the DNAD conte...

Page 167: ...ing this register unloads data from the appropriate byte lane of the DMA FIFO as determined by the FBL bits in the CTEST4 register Data written to the FIFO is loaded into the top of the FIFO Data read...

Page 168: ...transferred The maximum number of bytes transferred in any one Block Move command is 16 777 215 bytes The maximum value that can be loaded into the DMA Byte Counter DBC register is 0xFFFFFF If the ins...

Page 169: ...nstruction Set Registers 0x28 0x2B DMA Next Address DNAD Read Write DNAD DMA Next Address 31 0 This 32 bit register contains the general purpose address pointer At the start of some SCRIPTS operations...

Page 170: ...he next SCRIPTS command the Start DMA bit bit 2 DMA Con trol DCNTL register must be set each time the step interrupt occurs When writing this register eight bits at a time writing the upper eight bits...

Page 171: ...o in this mode Writes to the SCRATCHA register are unaffected Clearing the PCI Configuration Info Enable bit causes the SCRATCH A register to return to normal operation Register 0x38 DMA Mode DMODE Re...

Page 172: ...perations using the Memory Move instruction when a LSI53C1000 is I O mapped Bits 4 and 5 of the Chip Test Two CTEST2 register are used to determine the configuration status of the LSI53C1000 DIOM Dest...

Page 173: ...n indirect type the additional Dword is accessed in a subsequent bus ownership If the instruction is a table indirect block move type the chip accesses the remaining two Dwords in a subsequent bus own...

Page 174: ...d Setting a mask bit enables the assertion of INTA for the corresponding interrupt A masked nonfatal interrupt does not prevent unmasked or fatal interrupts from getting through interrupt stacking beg...

Page 175: ...register whichever contains the smaller value Clearing this bit disables the cache line size logic PFF Prefetch Flush 6 Setting this bit causes the prefetch unit to flush its contents This bit clears...

Page 176: ...his bit has no effect on the fetch mechanism from SCRIPTS RAM The prefetch unit does not support 64 bit data instruction fetches across the PCI bus Prefetches of SCRIPTS instructions are 32 bits in wi...

Page 177: ...of SCRIPTS after a single step interrupt R Reserved 1 COM LSI53C700 Family Compatibility 0 When the COM bit is cleared the LSI53C1000 behaves in a manner compatible with the LSI53C700 family selection...

Page 178: ...SCSI Phase Mismatch Initiator Mode SCSI ATN Condition Target Mode 7 In the initiator mode this bit is set when the SCSI phase asserted by the target and sampled during SREQ does not match the expecte...

Page 179: ...rflow occurs in initiator mode when an SREQ signal is received and causes the maximum offset as defined by the MO 5 0 bits in the SXFER register to be exceeded In initiator mode a phase change occurs...

Page 180: ...RST SCSI Reset Condition 1 This bit indicates assertion of the SRST signal by the LSI53C1000 or any other SCSI device This condition is edge triggered so multiple interrupts cannot occur because of a...

Page 181: ...LSI53C1000 is attempting to select or reselect does not respond within the programmed time out period See the description of the SCSI Timer Zero STIME0 register bits 3 0 for more information on the ti...

Page 182: ...Interrupt Status Zero SIST0 and SCSI Interrupt Status One SIST1 registers in any order insert a delay equivalent to 12 clock periods between the reads to ensure the interrupts clear properly Also if...

Page 183: ...Error condition The following conditions can result in a SCSI Gross Error Offset Underflow occurs in target mode when a SACK signal is received before the corresponding SREQ signal has been sent Offse...

Page 184: ...errupt even a valid SCSI disconnect This bit is also set if a selection time out occurs Since a selection time out is not considered an expected disconnect an unexpected disconnect may occur before at...

Page 185: ...is attempting to select or reselect does not respond within the programmed time out period See the description of the SCSI Timer Zero STIME0 register bits 3 0 for more information on the time out time...

Page 186: ...byte if the last byte received was never sent across the DMA bus It represents either the first data byte of a subsequent data transfer a residue byte which should be cleared when an Ignore Wide Resi...

Page 187: ...f the FE bit is set GPIO0 reflects when an internal opcode fetch is being performed GPIO0 goes low when an opcode fetch is performed When set the FE bit is independent of the setting of bit 0 GPIO0 If...

Page 188: ...n this timing is exceeded an interrupt is generated and the HTH bit in the SCSI Interrupt Status One SIST1 register is set The following table contains time out periods for the Handshake to Handshake...

Page 189: ...Setting this bit causes this timer to begin testing for SCSI REQ and ACK activity as soon as SBSY is asserted regardless of the agents participating in the transfer GENSF General Purpose Timer Scale F...

Page 190: ...ble delays the time value must be written to zero first and then written back to the desired value This is also required when changing from one time value to another Register 0x4A Response ID Zero RES...

Page 191: ...significant bit of RESPID0 represents ID 0 The SCID register still contains the chip ID used during arbitration The chip can respond to more than one ID because more than one bit can be set in the RES...

Page 192: ...SI Synchronous Offset Zero 1 This bit indicates that the current synchronous SREQ SACK offset is zero This bit is not latched and may change at any time It is used in low level synchronous SCSI operat...

Page 193: ...en cleared this bit powers down the internal quadrupler circuit Refer to Chapter 2 Functional Description for information concerning the operation of the quadrupler QSEL SCLK Quadrupler Select 2 This...

Page 194: ...t SCSI Offset 6 Setting this bit clears any outstanding synchronous SREQ SACK offset If a SCSI gross error occurs set this bit This bit automatically clears itself after resetting the synchronous offs...

Page 195: ...the SCSI bit level registers SCSI Output Data Latch SODL SCSI Bus Control Lines SBCL and input registers Register 0x4F SCSI Test Three STEST3 Read Write TE TolerANT Enable 7 Setting this bit enables...

Page 196: ...a single bit error on the SCSI bus is not interpreted as a single initiator response R Reserved 3 TTM Timer Test Mode 2 Asserting this bit facilitates testing of the selection time out general purpos...

Page 197: ...he SCSI data bus Reading this register causes the SCSI parity bit to be checked and causes a parity error interrupt if the data is invalid The power up values are indeterminate Register 0x52 SCSI Test...

Page 198: ...Registers 0x54 0x55 SCSI Output Data Latch SODL Read Write SODL SCSI Output Data Latch 15 0 This register is used primarily for diagnostic testing and programmed I O operations Data written to this re...

Page 199: ...e part and accounted for prior to taking the jump This feature does not cover however the byte that may appear in SCSI Wide Residue SWIDE This byte must be flushed manually This bit also enables the f...

Page 200: ...C Disable Auto FIFO Clear 4 This bit controls whether or not the FIFO is automatically cleared during a Data Out phase mismatch When set data in the DMA FIFO and data in the SCSI Output Data Latch SOD...

Page 201: ...for all master transactions DIS64SLV Disable 64 bit Slave Cycles 4 Setting this bit disables 64 bit slave data transfers to the SCRIPT RAM This causes only 32 bit data transfers to occur DDAC Disable...

Page 202: ...4 bit Direct BMOV 0 Setting this bit enables the 64 bit version of a direct BMOV When this bit is cleared direct BMOVs use the Static Block Move Selector SBMS register to obtain the upper 32 bits of t...

Page 203: ...erated because the upper byte lane parity is invalid Register 0x5A Chip Control Two CCNTL2 Read Write ShSGE Enable Shadowed SGE Register 7 Setting this bit allows access to the SGE Status registers sh...

Page 204: ...lative strength increase or decrease based on the LVDDL values Registers 0x5C 0x5F Scratch Register B SCRATCHB Read Write SCRATCHB Scratch Register B 31 0 This is a general purpose user definable scra...

Page 205: ...A3 Memory Move Read Selector MMRS Read Write MMRS Memory Move Read Selector 31 0 This register supplies AD 63 32 for data read operations during Memory to Memory Moves and absolute address LOAD operat...

Page 206: ...ring the PCI Configuration Info Enable bit causes the MMWS register to return to normal operation Registers 0xA8 0xAB SCRIPT Fetch Selector SFS Read Write SFS SCRIPT Fetch Selector 31 0 This register...

Page 207: ...32 during Table Indirect Fetches and Load and Store Data Structure Address DSA relative operations Registers 0xB0 0xB3 Static Block Move Selector SBMS Read Write SBMS Static Block Move Selector 31 0...

Page 208: ...cution of 64 bit direct BMOVs Registers 0xB8 0xBB DMA Next Address 64 DNAD64 Read Write DNAD64 DMA Next Address 64 31 0 This register holds the current selector being used in a host transaction The ap...

Page 209: ...3 the Disable AIP Code Generation bit in AIP Control One AIPCNTL1 R Reserved 5 4 XCLKH_DT Extra Clock of Data Hold on DT Transfer Edge 3 Setting this bit adds a clock of data hold to synchronous DT SC...

Page 210: ...data Refer to Table 4 4 and Table 4 5 for a summary of available transfer rates and to Figure 4 1 through Figure 4 3 for examples of how the XCLKS bits function Note This bit does not affect CRC timin...

Page 211: ...ST XCLKH_DT and XCLKH_ST bits Synchronous Send Rate Calculation The synchronous send rate in megatransfers s can be calculated using the following formula Send Rate DT Input Clock Rate SCFDivisor 2 XC...

Page 212: ...4 1 Single Transition Transfer Waveforms CLK1 REQ ACK DATA XCLKS_ST 0 XCLKH_ST 0 CLK1 REQ ACK DATA XCLKS_ST 1 XCLKH_ST 0 CLK1 REQ ACK DATA XCLKS_ST 0 XCLKH_ST 1 CLK1 REQ ACK DATA XCLKS_ST 1 XCLKH_ST 1...

Page 213: ...LK1 REQ ACK DATA CLK1 REQ ACK DATA CLK1 REQ ACK DATA CLK1 REQ ACK DATA XCLKS_DT 1 XCLKS_ST 1 XCLKH_DT 0 XCLKH_ST 0 1 CLK SCLK SCF Divisor XCLKS_DT 1 XCLKS_ST 0 XCLKH_DT 0 XCLKH_ST 0 XCLKS_DT 0 XCLKS_S...

Page 214: ...1 REQ ACK DATA CLK1 REQ ACK DATA CLK1 REQ ACK DATA CLK1 REQ ACK DATA XCLKS_DT 1 XCLKS_ST 1 XCLKH_DT 1 XCLKH_ST 1 1 CLK SCLK SCF Divisor XCLKS_DT 0 XCLKS_ST 0 XCLKH_DT 1 XCLKH_ST 1 XCLKS_DT 0 XCLKS_ST...

Page 215: ...40 00 26 67 160 2 3 12 50 40 00 22 86 160 2 4 12 50 40 00 20 00 160 3 0 18 75 26 67 26 67 160 3 1 18 75 26 67 21 33 160 3 2 18 75 26 67 17 78 160 3 3 18 75 26 67 15 24 160 3 4 18 75 26 67 13 33 160 4...

Page 216: ...0 4 3 100 00 5 00 2 86 40 4 4 100 00 5 00 2 50 40 8 0 200 00 2 50 2 50 40 8 1 200 00 2 50 2 00 40 8 2 200 00 2 50 1 67 40 8 3 200 00 2 50 1 43 40 8 4 200 00 2 50 1 25 1 Number Xclks XCLKS_DT XCLKS_ST...

Page 217: ...00 10 00 6 67 40 1 5 0 37 50 6 67 6 67 40 1 5 1 37 50 6 67 5 33 40 1 5 2 37 50 6 67 4 44 40 2 0 50 00 5 00 5 00 40 2 1 50 00 5 00 4 00 40 2 2 50 00 5 00 3 33 40 3 0 75 00 3 33 3 33 40 3 1 75 00 3 33...

Page 218: ...error status whether or not AIP checking is enabled This bit may indicate false errors and should not be used except for diagnostic purposes and when AIP Checking is enabled AIPERR AIP Error Status 1...

Page 219: ...nsfers RAIPERR Reset AIP Error 2 This bit allows an AIP error condition to be reset manually Setting this bit clears the AIP error status in bit 1 of AIP Control Zero AIPCNTL0 Setting this bit does no...

Page 220: ...ng when the phase mismatch occurred Registers 0xC4 0xC7 Phase Mismatch Jump Address Two PMJAD2 Read Write PMJAD2 Phase Mismatch Jump Address Two 31 0 This register contains the 32 bit address that is...

Page 221: ...rom the SCSI bus including any byte in SCSI Wide Residue SWIDE There is no data remaining in the part that must be flushed to memory with the exception of a possible byte in the SWIDE register That by...

Page 222: ...ounted for and any data left in the part is ignored and is automatically cleared from the FIFOs Registers 0xD0 0xD3 Entry Storage Address ESA Read Write ESA Entry Storage Address 31 0 This register s...

Page 223: ...from the SCSI bus during any given BMOV This value is used in calculating the information placed into the Remaining Byte Count RBC and Updated Address UA registers and should not need to be used in no...

Page 224: ...lative count of the number of bytes transferred across the SCSI bus during data phases It does not count bytes sent in command status Message In or Message Out phases It counts bytes as long as the ph...

Page 225: ...continues to calculate and send CRCs as requested by the target according to the SPI 3 specification DCRCPC Disable CRC Protocol Checking 6 Setting this bit causes the internal logic to neither check...

Page 226: ...g DT Data In SCSI transfers When this bit is cleared the SCSI control logic controls when the reseeding occurs TSTSD Test CRC Seed 4 Setting this bit causes the CRC logic to immediately reseed itself...

Page 227: ...contains the CRC calculation for that data if no CRC request occurred during the transfer In this mode this register is read only If CRCDSEL 0b01 this register represents the CRC Input register and co...

Page 228: ...0xF0 0xF1 DMA FIFO Byte Count DFBC Read Only DFBC DMA FIFO Byte Count 15 0 This 16 bit read only register contains the actual number of bytes contained in the DMA FIFO This register is not stable whi...

Page 229: ...r A SCRATCHA Read Write SCRATCHA Scratch Register A 31 0 When the Configuration Info Enable bit in the Chip Test Two CTEST2 register is set SCRATCH Register A is placed in the shadowed mode and return...

Page 230: ...trol Two CCNTL2 register SRP SCRIPTS RAM Parity 7 DFP DMA FIFO Parity 6 RD Residual Data in SCSI FIFO 5 PCO Phase Change with Outstanding Offset 4 OO Offset Overflow 3 OU Offset Underflow 2 DO Data Ov...

Page 231: ...rs 0x5C 0x5F Shadowed Scratch Register B SCRATCHB Read Write SCRATCHB Scratch Register B 31 0 When the PCI Configuration Info Enable bit in the Chip Test Two CTEST2 register is set SCRATCH Register B...

Page 232: ...gister to return to normal operation Registers 0xA4 0xA7 Shadowed Memory Move Write Selector MMWS Read Write MMWS Shadowed Memory Move Write Selector 31 0 When the PCI Configuration Info Enable bit in...

Page 233: ...ch Selector register is placed in shadow mode In this mode bits 23 16 of this register return the PCI Revision ID RID register value and bits 15 0 return the PCI Device ID register value when read Wri...

Page 234: ...4 124 Registers...

Page 235: ...gs or bus sequences to operate properly The following sections describe the benefits and use of SCSI SCRIPTS Section 5 1 SCSI SCRIPTS Section 5 2 Block Move Instructions Section 5 3 I O Instructions S...

Page 236: ...s of SCRIPTS instructions are implemented in the LSI53C1000 Block Move used to move data between the SCSI bus and memory I O or Read Write causes the LSI53C1000 to trigger common SCSI hardware sequenc...

Page 237: ...in the DMA FIFO to transfer a programmable size block of data For a SCSI receive operation it waits until enough data is collected in the DMA FIFO for transfer to memory At this point the LSI53C1000...

Page 238: ...DMA Mode DMODE register determine whether the source destination address resides in memory or I O space When data is moved onto the System Processor System Memory or Internal RAM SCSI Initiator Write...

Page 239: ...oved to or from the 32 bit data start address for the Block Move instruction The value is loaded into the chip s address register and incremented as data is transferred The address of the data to move...

Page 240: ...compiler the table offset is placed in the SCRIPT at compile time Then at the actual data transfer time the offsets are added to the base address of the data address table by the external processor Th...

Page 241: ...generate the address of the required data both positive and negative offsets are allowed A subsequent fetch from that address brings the data values into the chip For a MOVE instruction the 24 bit byt...

Page 242: ...tor for the upper 32 bit address Please see the Table Indirect Index mode mapping table for a breakdown of index values and the corresponding registers selected The selected address is automatically l...

Page 243: ...BMS 1 0 ScratchC J MMWS MMRS SFS DRS SBMS DBMS 1 1 1st Table Entry Dword bits 31 24 40 bit addressing only Index Value Selector Used 0x00 Scratch C 0x01 Scratch D 0x02 Scratch E 0x03 Scratch F 0x04 Sc...

Page 244: ...is a vendor unique code the LSI53C1000 overwrites the DMA Byte Counter DBC register with the length of the Command Descriptor Block 6 10 or 12 bytes If the VUE0 bit is set the LSI53C1000 receives the...

Page 245: ...d for which the LSI53C1000 has not yet transferred data by responding with a SACK The LSI53C1000 compares the SCSI phase bits in the DMA Command DCMD register with the latched SCSI phase lines stored...

Page 246: ...he desired SCSI information transfer phase When the LSI53C1000 operates in the initiator mode these bits are compared with the latched SCSI phase bits in the SCSI Status One SSTAT1 register When the L...

Page 247: ...Figure 5 3 Block Move Instruction Second Dword Start Address 31 0 This 32 bit field specifies the starting address of the data to move to from memory This field is copied to the DMA Next Address DNAD...

Page 248: ...is divided into First Dword and Second Dword 5 3 1 First Dword This section describes the first Dword of the I O Instruction register Figure 5 5 First 32 bit Word of the I O Instruction IT 1 0 Instruc...

Page 249: ...n before the reselection completes It continues executing SCRIPTS until a SCRIPT that requires a response from the initiator is encountered If the LSI53C1000 is selected or reselected before winning a...

Page 250: ...set SACK or SATN except for testing purposes When the target bit is set the corresponding bit in the SCSI Control Zero SCNTL0 register is also set When the carry bit is set the corresponding bit in t...

Page 251: ...t instruction from the address pointed to by the 32 bit jump address field stored in the DMA Next Address DNAD register Manually set the LSI53C1000 to the initiator mode if it is reselected or to the...

Page 252: ...he ALU is cleared RA Relative Addressing Mode 26 When this bit is set the 24 bit signed value in the DMA Next Address DNAD register is used as a relative displacement from the current DMA SCRIPTS Poin...

Page 253: ...dress An I O command structure must have all four bytes contiguous in system memory as shown below The offset period bits are ordered as in the SCSI Transfer SXFER register The configuration bits are...

Page 254: ...fetch address Sel Select with ATN 24 This bit specifies whether SATN is asserted during the selection phase when the LSI53C1000 is executing a Select instruction When operating in the initiator mode...

Page 255: ...et Clear SACK 6 This bit is used in conjunction with a Set or Clear instruction to assert or deassert SACK The Set instruction is used to assert SACK on the SCSI bus The Clear instruction is used to d...

Page 256: ...e initiator the opportunity to assert attention before acknowledging the last message byte For example if the initiator wishes to reject a message it issues an Assert SCSI ATN instruction before a Cle...

Page 257: ...bits 26 24 in conjunction with the opcode bits to determine which instruction is currently selected OPC 2 0 Opcode 29 27 These bits determine if the instruction is a Read Write or an I O instruction O...

Page 258: ...Destination Address 31 0 This field contains the 32 bit destination address where the data is to move 5 4 3 Read Modify Write Cycles During these cycles the register is read the selected operation is...

Page 259: ...structions1 Operator Opcode 111 Read Modify Write Opcode 110 Move to SFBR Opcode 101 Move from SFBR 000 Move data into register Syntax Move data8 to RegA Move data into SCSI First Byte Received SFBR r...

Page 260: ...e the result in the register Syntax Move SFBR SHR RegA 110 Add data to register without carry and place the result in the same register Syntax Move RegA data8 to RegA Add data to register without carr...

Page 261: ...hey can be dependent on a true false comparison of the ALU Carry bit or a comparison of the SCSI information transfer phase with the Phase field and or a comparison of the First Byte Received with the...

Page 262: ...ons are true it loads the DMA SCRIPTS Pointer DSP register with the contents of the DMA SCRIPTS Pointer Save DSPS register and that address value becomes the address of the next instruction When the L...

Page 263: ...y asserting the INT signal The 32 bit address field stored in the DMA SCRIPTS Pointer Save DSPS register can contain a unique interrupt service vector When servicing the interrupt this unique status c...

Page 264: ...ext instruction and not the one currently executing The relative mode does not apply to Return and Interrupt SCRIPTS Jump Call an Absolute Address Start execution at the new absolute address Jump Call...

Page 265: ...ime alteration of physical addresses and can be stored in and executed from a PROM J 32 64 Bit Jump 22 When this bit is cleared the jump address is 32 bits wide When this bit is set the jump address i...

Page 266: ...the compare occurs When the LSI53C1000 is operating in the target mode and this bit is set it tests for an active SCSI SATN signal VP Wait For Valid Phase 16 If the Wait for Valid Phase bit is set th...

Page 267: ...trol Instructions Second Dword Jump Address 31 0 This 32 bit field contains the address of the next instruction to fetch when a jump is taken Once the LSI53C1000 fetches the instruction from the addre...

Page 268: ...mory moves frees the system processor for other tasks and moves data at higher speeds than available from current DMA controllers Up to 16 Mbytes may be transferred with one instruction There are two...

Page 269: ...er 2 Func tional Description TC 23 0 Transfer Count 23 0 The number of bytes to transfer is stored in the lower 24 bits of the first instruction word 5 6 1 Read Write System Memory from a SCRIPT By us...

Page 270: ...restrictions apply to register access operations as to normal memory to memory transfers 5 6 2 Second Dword This section describes the second Dword of the Memory Move Instruction register Figure 5 13...

Page 271: ...alues The second Dword contains the DMA SCRIPTS Pointer Save DSPS value This is either the actual memory location of where to load store or the offset from the Data Structure Address DSA depending on...

Page 272: ...I commands for I O read and I O write to access the I O space 5 7 1 First Dword This section describes the first Dword of the Load and Store Instruction register Figure 5 15 Load and Store Instruction...

Page 273: ...Store instruction automatically flushes the prefetch unit Use No Flush if the source and destination are not within four instructions of the current Store instruction This bit has no effect on the Loa...

Page 274: ...econd Dword Memory I O Address DSA Offset 31 0 This is the actual memory location of where to load store or the offset from the Data Structure Address DSA register value 31 24 23 16 15 8 7 0 DSPS Regi...

Page 275: ...stics Section 6 2 TolerANT Technology Electrical Characteristics Section 6 3 AC Characteristics Section 6 4 PCI and External Memory Interface Timing Diagrams Section 6 5 SCSI Timing Diagrams Section 6...

Page 276: ...4 5 V VIN Input voltage 0 3 5 55 V VIN PCI Input voltage PCI pins 5 5 11 0 V ILP 2 2 2 V VPIN 8 V Latch up current 150 mA T Lead temperature 250 C 10 seconds ESD3 3 SCSI pins only Electrostatic disch...

Page 277: ...ate IO Sink current 9 6 14 4 mA Asserted state IO Source current 6 4 9 6 mA Negated state IO Sink current 6 4 9 6 mA Negated state IOZ 3 state leakage 20 A RL 2 VCM IO RL 2 IO Table 6 4 LVD Receiver S...

Page 278: ...VSS 0 35 0 5 V Note 1 IOZ 3 state leakage 10 10 A 0 VDD 3 Max 1 Functional test specified VIH VIL for each mode Table 6 6 Input Capacitance Symbol Parameter Min Max Unit Test Conditions CI Input capac...

Page 279: ...A Bidirectional Signals MAD 7 0 Symbol Parameter Min Max Unit Test Conditions VIH Input high voltage 2 0 5 55 V VIL Input low voltage 0 3 0 8 V VOH Output high voltage 2 4 VDD V 4 mA VOL Output low vo...

Page 280: ...0 and C_BE 3 0 25 A Table 6 11 Input Signals1 CLK GNT IDSEL INT_DIR RST SCLK TCK TDI TEST_HSC TEST_RST TEST_PD TMS 1 Pull text does not apply to CKL GNT IDSEL RST and SCLK Symbol Parameters Min Max U...

Page 281: ...Technology Electrical Characteristics for SE SCSI Signals1 Symbol Parameter Min Max Units Test Conditions VOH 2 Output high voltage 2 2 3 7 V IOH 7 mA VOL Output low voltage 0 0 0 5 V IOL 48 mA VIH In...

Page 282: ...elay 20 30 ns Figure 6 4 Ultra filter delay 10 15 ns Figure 6 4 Ultra2 filter delay 5 8 ns Figure 6 4 Extended filter delay 40 60 ns Figure 6 4 1 These values are guaranteed by periodic characterizati...

Page 283: ...Hysteresis of SCSI Receivers Figure 6 6 Input Current as a Function of Input Voltage 1 0 Received Logic Level Input Voltage Volts 1 1 1 3 1 5 1 7 40 20 0 20 40 4 0 4 8 12 16 0 7 V 8 2 V HIGH Z OUTPUT...

Page 284: ...re 6 7 Output Current as a Function of Output Voltage Output Sink Current milliAmperes 0 200 400 600 800 0 1 2 3 4 5 Output Voltage Volts Output Source Current milliAmperes Output Voltage Volts 0 1 2...

Page 285: ...e of 50 pF Table 6 14 and Figure 6 8 provide external clock timing data Figure 6 8 External Clock Table 6 14 External Clock Symbol Parameter 66 MHz PCI 33 MHz PCI1 Units Min Max Min Max t1 PCI Bus clo...

Page 286: ...6 15 Reset Input Symbol Parameter Min Max Units t1 Reset pulse width 10 tCLK t2 Reset deasserted setup to CLK HIGH 0 ns t3 MAD setup time to CLK HIGH for configuring the MAD bus only 20 ns t4 MAD hold...

Page 287: ...oup applies to Target Timing The second group applies to Initiator Timing The third group applies to External Memory Timing Note Multiple byte accesses to the external memory bus increase the read or...

Page 288: ...Bit Address and Data Burst Write 64 Bit Address and Data External Memory Timing External Memory Read External Memory Write Normal Fast Memory 128 Kbytes Single Byte Access Read Cycle Normal Fast Memor...

Page 289: ...signal input hold time 0 0 ns t3 CLK to shared signal output valid 2 6 2 11 ns Data Out Byte Enable Addr In CMD t2 In Out t1 t2 t1 t3 t2 t1 t1 t2 t2 t3 t3 t2 t1 t3 t2 t1 CLK Driven by System FRAME Dri...

Page 290: ...2 Shared signal input hold time 0 0 ns t3 CLK to shared signal output valid 2 6 2 11 ns Data In Byte Enable Addr In CMD t2 t1 t2 t1 t2 t1 t1 t2 t2 t3 t2 t1 t3 t2 t1 CLK Driven by System FRAME Driven b...

Page 291: ...etup time 3 7 ns t2 Shared signal input hold time 0 0 ns t3 CLK to shared signal output valid 2 6 2 11 ns Data Byte Enable Addr In CMD t2 t1 t2 t1 t2 t1 t1 t2 t2 t3 t2 t1 t3 CLK Driven by System FRAME...

Page 292: ...perating Register SCRIPTS RAM Read 64 Bits Symbol Parameter 66 MHz PCI 33 MHz PCI Unit Min Max Min Max t1 Shared signal input setup time 3 7 ns t2 Shared signal input hold time 0 0 ns t3 CLK to shared...

Page 293: ...C_BE 3 0 Driven by Master PAR PAR64 Driven by Master Addr IRDY Driven by Master TRDY Driven by LSI53C1000 STOP Driven by LSI53C1000 DEVSEL Driven by LSI53C1000 Out t3 In Out t3 LSI53C1000 Data LSI53C...

Page 294: ...perating Register SCRIPTS RAM Read 32 Bits Symbol Parameter 66 MHz PCI 33 MHz PCI Unit Min Max Min Max t1 Shared signal input setup time 3 7 ns t2 Shared signal input hold time 0 0 ns t3 CLK to shared...

Page 295: ...ts Byte Enable Addr In CMD t2 t1 t2 t1 t2 t1 t1 t2 t2 t3 t2 t1 t3 CLK Driven by System FRAME Driven by Master AD 31 0 Driven by Master C_BE 3 0 Driven by Master PAR Driven by Master IRDY Driven by Mas...

Page 296: ...erating Register SCRIPTS RAM Write 64 Bits Symbol Parameter 66 MHz PCI 33 MHz PCI Unit Min Max Min Max t1 Shared signal input setup time 3 7 ns t2 Shared signal input hold time 0 0 ns t3 CLK to shared...

Page 297: ...AD 31 0 Driven by Master C_BE 3 0 Driven by Master PAR PAR64 Driven by Master IRDY Driven by Master TRDY Driven by LSI53C1000 STOP Driven by LSI53C1000 DEVSEL Driven by LSI53C1000 In In t1 t2 Addr Lo...

Page 298: ...Fetch 32 Bit Address and Data Symbol Parameter 66 MHz PCI 33 MHz PCI Unit Min Max Min Max t1 Shared signal input setup time 3 7 ns t2 Shared signal input hold time 0 0 ns t3 CLK to shared signal outp...

Page 299: ...by LSI53C1000 PAR Driven by LSI53C1000 IRDY Driven by LSI53C1000 TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target t1 t6 t3 AD 31 0 Driven by LSI53C1000 C_BE 3 0 Driven by LSI53C1000...

Page 300: ...MHz PCI 33 MHz PCI Unit Min Max Min Max t1 Shared signal input setup time 3 7 ns t2 Shared signal input hold time 0 0 ns t3 CLK to shared signal output valid 2 6 2 11 ns t4 Side signal input setup tim...

Page 301: ...ven by LSI53C1000 PAR Driven by LSI53C1000 IRDY Driven by LSI53C1000 TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target t1 t6 t3 AD 31 0 Driven by LSI53C1000 C_BE 3 0 Driven by LSI53C...

Page 302: ...Hz PCI 33 MHz PCI Unit Min Max Min Max t1 Shared signal input setup time 3 7 ns t2 Shared signal input hold time 0 0 ns t3 CLK to shared signal output valid 2 6 2 11 ns t4 Side signal input setup time...

Page 303: ...LSI53C1000 PAR Driven by LSI53C1000 IRDY Driven by LSI53C1000 TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target t1 t6 t3 AD 31 0 Driven by LSI53C1000 C_BE 3 0 Driven by LSI53C1000 t3...

Page 304: ...MHz PCI 33 MHz PCI Unit Min Max Min Max t1 Shared signal input setup time 3 7 ns t2 Shared signal input hold time 0 0 ns t3 CLK to shared signal output valid 2 6 2 11 ns t4 Side signal input setup tim...

Page 305: ...en by LSI53C1000 PAR Driven by LSI53C1000 IRDY Driven by LSI53C1000 TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target t6 t3 AD 31 0 Driven by LSI53C1000 C_BE 3 0 Driven by LSI53C1000...

Page 306: ...27 Burst Read 32 Bit Address and Data Symbol Parameter 66 MHz PCI 33 MHz PCI Unit Min Max Min Max t1 Shared signal input setup time 3 7 ns t2 Shared signal input hold time 0 0 ns t3 CLK to shared sign...

Page 307: ...GPIO1_MASTER Driven by LSI53C1000 REQ Driven by LSI53C1000 PAR Driven by LSI53C1000 IRDY Driven by LSI53C1000 TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target AD 31 0 Driven by LSI...

Page 308: ...28 Burst Read 64 Bit Address and Data Symbol Parameter 66 MHz PCI 33 MHz PCI Unit Min Max Min Max t1 Shared signal input setup time 3 7 ns t2 Shared signal input hold time 0 0 ns t3 CLK to shared sign...

Page 309: ...ven by LSI53C1000 TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target AD 31 0 Driven by LSI53C1000 C_BE 3 0 Driven by LSI53C1000 t3 GNT Driven by Arbiter FRAME Driven by LSI53C1000 Add...

Page 310: ...29 Burst Write 32 Bit Address and Data Symbol Parameter 66 MHz PCI 33 MHz PCI Unit Min Max Min Max t1 Shared signal input setup time 3 7 ns t2 Shared signal input hold time 0 0 ns t3 CLK to shared sig...

Page 311: ...by LSI53C1000 GPIO1_MASTER Driven by LSI53C1000 REQ Driven by LSI53C1000 PAR Driven by LSI53C1000 IRDY Driven by LSI53C1000 TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target AD 31 0...

Page 312: ...30 Burst Write 64 Bit Address and Data Symbol Parameter 66 MHz PCI 33 MHz PCI Unit Min Max Min Max t1 Shared signal input setup time 3 7 ns t2 Shared signal input hold time 0 0 ns t3 CLK to shared sig...

Page 313: ...000 IRDY Driven by LSI53C1000 TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target AD 31 0 Driven by LSI53C1000 C_BE 3 0 Driven by LSI53C1000 t3 GNT Driven by Arbiter FRAME Driven by LS...

Page 314: ...6 40 Specifications This page intentionally left blank...

Page 315: ...Max t1 Shared signal input setup time 3 7 ns t2 Shared signal input hold time 0 0 ns t3 CLK to shared signal output valid 2 6 2 11 ns t11 Address setup to MAS HIGH 25 25 ns t12 Address hold from MAS...

Page 316: ...ster Addr C_BE 3 0 Driven by Master FRAME Driven by Master Data Driven by Memory 1 2 3 4 5 6 7 8 9 10 LSI53C1000 Data Addr In Byte Enable LSI53C1000 Data MAD Addr driven by LSI53C1000 High Order Addre...

Page 317: ...0 DEVSEL Driven by LSI53C1000 AD 31 0 Driven by Master Addr C_BE 3 0 Driven by Master FRAME Driven by Master Data Driven by Memory 11 12 13 14 15 16 17 18 19 20 LSI53C1000 Data Data Out LSI53C1000 Dat...

Page 318: ...6 44 Specifications This page intentionally left blank...

Page 319: ...ns t3 CLK to shared signal output valid 2 6 2 11 ns t11 Address setup to MAS HIGH 25 25 ns t12 Address hold from MAS HIGH 15 15 ns t13 MAS pulse width 25 25 ns t20 Data setup to MWE LOW 30 30 ns t21...

Page 320: ...by Master FRAME Driven by Master 1 2 3 4 5 6 7 8 9 10 Addr In MAD Driven by LSI53C1000 High Order Address Middle Order Address Low Order Address MAS1 Driven by LSI53C1000 MAS0 Driven by LSI53C1000 MCE...

Page 321: ...STOP Driven by LSI53C1000 DEVSEL Driven by LSI53C1000 AD 31 0 C_BE 3 0 Driven by Master FRAME Driven by Master 11 12 13 14 15 16 17 18 19 20 MAD Driven by LSI53C1000 MAS1 Driven by LSI53C1000 MAS0 Dri...

Page 322: ...ed in 150 ns t15 Address valid to data clocked in 205 ns t16 MOE LOW to data clocked in 100 ns t17 Data hold from address MOE MCE change 0 ns t18 Address out from MOE MCE HIGH 50 ns t19 Data setup to...

Page 323: ...e Byte Access Read Cycle Cont CLK Driven by System Data Driven by Memory 11 12 13 14 15 16 17 18 19 20 MAD Addr driven by LSI53C1000 MAS1 Driven by LSI53C1000 MAS0 Driven by LSI53C1000 MCE Driven by L...

Page 324: ...tup to MWE LOW 30 ns t21 Data hold from MWE HIGH 20 ns t22 MWE pulse width 100 ns t23 Address setup to MWE LOW 60 ns t24 MCE LOW to MWE HIGH 120 ns t25 MCE LOW to MWE LOW 25 ns t26 MWE HIGH to MCE HIG...

Page 325: ...ytes Single Byte Access Write Cycle Cont CLK Driven by System 11 12 13 14 15 16 17 18 19 20 MAD Driven by LSI53C1000 MAS1 Driven by LSI53C1000 MAS0 Driven by LSI53C1000 MCE Driven by LSI53C1000 MOE Dr...

Page 326: ...by LSI53C1000 AD 31 0 Driven by LSI53C1000 C_BE 3 0 Driven by Master FRAME Driven by Master Master Addr Data Master Addr Data MAD Addr Driven by LSI53C1000 MAS1 Driven by LSI53C1000 MAS0 Driven by LS...

Page 327: ...LSI53C1000 DEVSEL Driven by LSI53C1000 AD 31 0 Driven by LSI53C1000 C_BE 3 0 Driven by Master FRAME Driven by Master Master Addr Data Master Addr Data MAD Addr Driven by LSI53C1000 MAS1 Driven by LSI5...

Page 328: ...iven by LSI53C1000 AD 31 0 C_BE 3 0 Driven by Master FRAME Driven by Master MAD Driven by LSI53C1000 MAS1 Driven by LSI53C1000 MAS0 Driven by LSI53C1000 MCE Driven by LSI53C1000 MOE Driven by LSI53C10...

Page 329: ...1000 STOP Driven by LSI53C1000 DEVSEL Driven by LSI53C1000 AD 31 0 C_BE 3 0 Driven by Master FRAME Driven by Master MAD Driven by LSI53C1000 MAS1 Driven by LSI53C1000 MAS0 Driven by LSI53C1000 MCE Dri...

Page 330: ...ss valid to data clocked in 205 ns t16 MOE LOW to data clocked in 100 ns t17 Data hold from address MOE MCE change 0 ns t18 Address out from MOE MCE HIGH 50 ns t19 Data setup to CLK HIGH 5 ns CLK Driv...

Page 331: ...ead Cycle Cont CLK Driven by System Data Driven by Memory 11 12 13 14 15 16 17 18 19 20 MAD Addr driven by LSI53C1000 MAS1 Driven by LSI53C1000 MAS0 Driven by LSI53C1000 MCE Driven by LSI53C1000 MOE D...

Page 332: ...ata hold from MWE HIGH 20 ns t22 MWE pulse width 100 ns t23 Address setup to MWE LOW 60 ns t24 MCE LOW to MWE HIGH 120 ns t25 MCE LOW to MWE LOW 25 ns t26 MWE HIGH to MCE HIGH 25 ns CLK Driven by Syst...

Page 333: ...128 Kbytes Write Cycle Cont CLK Driven by System 11 12 13 14 15 16 17 18 19 20 MAD Driven by LSI53C1000 MAS1 Driven by LSI53C1000 MAS0 Driven by LSI53C1000 MCE Driven by LSI53C1000 MOE Driven by LSI53...

Page 334: ...cked in 205 ns t16 MOE LOW to data clocked in 100 ns t17 Data hold from address MOE MCE change 0 ns t18 Address out from MOE MCE HIGH 50 ns t19 Data setup to CLK HIGH 5 ns CLK Driven by System 1 2 3 4...

Page 335: ...ns t21 Data hold from MWE HIGH 20 ns t22 MWE pulse width 100 ns t23 Address setup to MWE LOW 60 ns t24 MCE LOW to MWE HIGH 120 ns t25 MCE LOW to MWE LOW 25 ns t26 MWE HIGH to MCE HIGH 25 ns CLK Drive...

Page 336: ...gure 6 35 Initiator Asynchronous Send Table 6 39 Initiator Asynchronous Send Symbol Parameter Min Max Units t1 SACK asserted from SREQ asserted 5 ns t2 SACK deasserted from SREQ deasserted 5 ns t3 Dat...

Page 337: ...easserted 5 ns t3 Data setup to SREQ asserted 0 ns t4 Data hold from SACK asserted 0 ns Valid n Valid n 1 n 1 n 1 n n t1 t2 t3 t4 SREQ SACK SD 15 0 SDP 1 0 Table 6 41 Target Asynchronous Send Symbol P...

Page 338: ...4 SREQ SACK SD 15 0 SDP 1 0 Table 6 43 SCSI 1 Transfers SE 5 0 Mbytes Symbol Parameter Min Max Units tST1 Send SREQ or SACK assertion pulse width 80 ns tST2 Send SREQ or SACK deassertion pulse width 8...

Page 339: ...rted 14 ns tST6 Receive data hold from SREQ or SACK asserted 24 ns Table 6 45 Ultra SCSI SE Transfers 20 0 Mbytes 8 Bit Transfers or 40 0 Mbytes 16 Bit Transfers Quadrupled 40 MHz Clock1 1 Note For fa...

Page 340: ...8 ns tST2 Send SREQ or SACK deassertion pulse width 8 ns tST1 Receive SREQ or SACK assertion pulse width 6 5 ns tST2 Receive SREQ or SACK deassertion pulse width 6 5 ns tST3 Send data setup to SREQ or...

Page 341: ...T6 Receive data hold from SREQ transition 10 ns tDT7 Send CRC Request Setup to SREQ transition 50 ns tDT8 Send CRC Request Hold to SREQ transition 40 ns tDT9 Receive CRC Request Setup to SREQ transiti...

Page 342: ...nsfers 40 0 Mbyte 8 Bit Transfers or 80 0 Mbyte 16 Bit Transfers Quadrupled 40 MHz Clock Symbol Parameter Min Max Unit tDT1 Send SREQ assertion pulse width 23 ns tDT2 Send SREQ deassertion pulse width...

Page 343: ...ns tDT3 Send data setup to SREQ transition 5 ns tDT4 Send data hold from SREQ transition 5 ns tDT5 Receive data setup to SREQ transition 1 25 ns tDT6 Receive data hold from SREQ transition 1 25 ns tD...

Page 344: ...6 70 Specifications This page intentionally left blank...

Page 345: ...strates the signal locations on the 329 Ball Grid Array BGA Table 6 51 and Table 6 52 list all the signal names alphabetically and by BGA position Figure 6 42 illustrates the LSI53C1000 329 BGA Figure...

Page 346: ...D30 AD29 J K C_BE3 AD24 AD26 VDD_IO VSS_IO VSS_IO VSS_IO K L AD23 AD22 IDSEL AD25 VSS_IO VSS_IO VSS_IO L M AD21 AD19 AD20 VSS_IO VSS_IO VSS_IO VSS_IO M N AD17 AD18 AD16 IRDY VSS_IO VSS_IO VSS_IO N P C...

Page 347: ...H NC NC NC NC H J NC NC NC NC J K VSS_IO VSS_IO VDD_IO NC NC NC K L VSS_IO VSS_IO NC NC NC NC L M VSS_IO VSS_IO VSS_IO RBIAS VDD_ BIAS NC M N VSS_IO VSS_IO NC NC NC NC N P VSS_IO VSS_IO VDD_IO NC NC N...

Page 348: ...V22 NC V23 NC W20 NC W21 NC W22 NC W23 NC Y21 NC Y22 NC Y23 PAR T1 PAR64 AA5 PERR R4 RBIAS M21 REQ H2 REQ64 AA2 RESERVED AB14 RST G1 SACK C13 SACK A14 SATN B11 SATN B12 SBSY C12 SBSY A12 SC_D C15 SC_...

Page 349: ..._IO D10 SD7 D11 VSS_IO D12 SRST D13 VDD_IO D14 SSEL D15 NC D16 VDD_IO D17 SD9 D18 SD11 D19 VSS_IO D20 VSS_CORE D21 NC D22 NC D23 TDO E1 TDI E2 TMS E3 VDD_CORE E4 NC E20 NC E21 NC E22 NC E23 ALT_INTA F...

Page 350: ...6 76 Specifications Figure 6 42 LSI53C1000 329 Ball Grid Array Bottom view...

Page 351: ...A Mechanical Drawing Important This drawing may not be the latest version For board layout and manufacturing obtain the most recent engineering drawings from your LSI Logic marketing representative by...

Page 352: ...6 78 Specifications...

Page 353: ...Read Write 4 11 Base Address Register Two BAR2 MEMORY 0x18 0x1B Read Write 4 10 Base Address Register Zero BAR0 I O 0x10 0x13 Read Write 4 9 Bridge Support Extensions PMCSR_BSE 0x46 Read Only 4 20 Cac...

Page 354: ...t Control Status PMCSR 0x44 0x45 Read Write 4 19 Reserved 0x0F 4 9 Reserved 0x24 0x27 4 12 Reserved 0x28 0x2B 4 12 Reserved 0x35 0x37 4 15 Reserved 0x38 0x3B 4 15 Revision ID RID 0x08 Read Only 4 6 St...

Page 355: ...Control Zero CCNTL0 0x56 Read Write 4 89 Chip Test Five CTEST5 0x22 Read Write 4 56 Chip Test Four CTEST4 0x21 Read Write 4 55 Chip Test One CTEST1 0x19 Read Only 4 51 Chip Test Six CTEST6 0x23 Read...

Page 356: ...4 46 Mailbox One MBOX1 0x17 Read Write 4 50 Mailbox Zero MBOX0 0x16 Read Write 4 50 Memory Move Read Selector MMRS 0xA0 0xA3 Read Write 4 95 Memory Move Write Selector MMWS 0xA4 0xA7 Read Write 4 96 R...

Page 357: ...I Interrupt Enable One SIEN1 0x41 Read Write 4 70 SCSI Interrupt Enable Zero SIEN0 0x40 Read Write 4 68 SCSI Interrupt Status One SIST1 0x43 Read Only 4 75 SCSI Interrupt Status Zero SIST0 0x42 Read O...

Page 358: ...yte Value CRCPAD 0xE0 0xE1 Read Write 4 115 Cumulative SCSI Byte Count CSBC 0xDC 0xDF Read Write 4 114 DMA FIFO Byte Count DFBC 0xF0 0xF1 Read Only 4 118 Entry Storage Address ESA 0xD0 0xD3 Read Write...

Page 359: ...wed Scratch Register A SCRATCHA 0x34 0x37 Read Write 4 119 Shadowed Scratch Register B SCRATCHB 0x5C 0x5F Read Write 4 121 Shadowed SCRIPT Fetch Selector SFS 0xA8 0xAB Read Write 4 123 Shadowed SCSI I...

Page 360: ...A 8 Register Summary...

Page 361: ...emory interface diagrams Figure B 1 16 Kbyte Interface with 200 ns Memory LSI53C1000 27C128 MOE OE MCE CE D 7 0 8 MAD 7 0 Bus CK Q 7 0 8 A 7 0 QE D 5 0 CK Q 5 0 QE 6 A 13 8 6 VDD MAS0 MAS1 8 Note MAD...

Page 362: ...0 8 MAD 7 0 Bus CK Q 7 0 8 A 7 0 QE D 7 0 CK Q 7 0 QE 8 A 15 8 8 VDD MAS0 MAS1 8 Note MAD 3 1 0 pulled LOW internally MAD bus sense logic enabled for 64 Kbyte of fast memory 150 ns devices 66 MHz HCT...

Page 363: ...Q 7 0 QE 8 A 15 8 8 VDD MAS0 MAS1 8 Note MAD 2 0 pulled LOW internally MAD bus sense logic enabled for 128 256 512 Kbytes or 1 Mbyte of fast memory 150 ns devices 66 MHz The HCT374s may be replaced wi...

Page 364: ...d for 512 Kbytes of slow memory 150 ns devices additional time required for HCT139 66 MHz The HCT374s may be replaced with HCT377s HCT374 HCT374 GPIO4 MWE VPP Control 12 V VPP Optional for Flash Memor...

Page 365: ...CIO 4 52 CLF 2 51 4 54 CLS 7 0 4 7 CLSE 2 7 4 65 CM 4 52 CMP 4 68 4 72 CON 4 28 4 47 CP 5 32 CP 7 0 4 15 CSBC 4 114 CSF 2 51 4 86 CT 5 31 CTEST0 4 51 CTEST1 4 51 CTEST2 4 52 CTEST3 4 53 CTEST4 4 55 CT...

Page 366: ...MDPE 4 40 4 64 ME 4 77 MEMORY 4 10 4 11 MG 7 0 4 17 ML 7 0 4 17 MMRS 4 95 4 122 MMWS 4 96 4 122 MO 5 0 4 33 MPEE 4 55 MSG 4 37 4 39 4 43 NC 4 6 NF 5 35 5 39 NIP 7 0 4 18 O 2 0 5 23 OLF 4 42 OLF1 4 44...

Page 367: ...SCRIPTS 2 20 64 Kbytes ROM read cycle 6 60 6 61 64 bit table indirect indexing mode 64TIMOD 4 91 A A and B DIFFSENS SCSI signals 6 4 A 6 0 5 24 A_DIFFSENS 3 11 A_GPIO0_ FETCH 3 13 A_GPIO1_ MASTER 3 1...

Page 368: ...9 control 1 CCNTL1 4 91 test five CTEST5 2 7 4 56 test four CTEST4 2 34 4 55 test one CTEST1 4 51 test six CTEST6 4 57 test three CTEST3 2 9 2 12 4 53 test two CTEST2 4 52 test zero CTEST0 4 51 CHMOV...

Page 369: ...EN64TIBMV 4 92 AIP 4 99 asynchronous information protection 4 99 bus mastering EBM 4 4 I O space EIS 4 4 jump on nondata phase mismatches ENNDJ 4 90 memory space EMS 4 4 parity checking 2 33 checking...

Page 370: ...transfer control instruction 5 27 INTA 2 46 2 52 INTC 2 53 interface 128 256 512 Kbyte or 1 Mbyte 150 ns memory B 3 16 Kbyte 200 ns memory B 1 512 Kbyte 150 ns memory B 4 64 Kbyte 150 ns memory B 2 co...

Page 371: ...nd 2 6 read line 2 12 2 13 read line command 2 8 read multiple 2 12 2 13 read multiple command 2 7 space 2 3 2 4 to memory 2 18 to memory moves 2 18 write 2 12 2 13 write and invalidate 2 12 write and...

Page 372: ...write system memory from a SCRIPT 5 35 read write instructions 5 23 5 25 system memory from a SCRIPT 5 35 receive rate calculation 2 43 received master abort from master RMA 4 5 target abort from mas...

Page 373: ...pare phase 5 32 data compare mask 5 32 data compare value 5 33 instruction type 5 27 interrupt on the fly 5 31 jump address 5 33 jump if true false 5 31 jump64 address 5 33 opcode 5 27 relative addres...

Page 374: ...ng selection 2 40 instruction 5 17 with ATN 5 20 with SATN on a start sequence WATN 4 25 selected SEL 4 69 4 73 selection or reselection time out STO 4 71 4 75 selection response logic test SLT 4 82 s...

Page 375: ...CRIPTS instruction prefetching 2 32 count 5 35 counter 5 12 information 2 18 period factor 2 24 rate synchronous 2 41 width exponent 2 24 TRDY 2 10 3 7 U Ultra 160 m features 2 22 Ultra SCSI single en...

Page 376: ...IX 12 Index...

Page 377: ...comments and fax it to us at the number shown If appropriate please also fax copies of any marked up pages from this document Important Please include your name phone number fax number and company ad...

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Page 381: ...Tel 317 984 8608 Ligonier R A Tel 219 894 3184 Plainfield R A Tel 317 838 0360 Massachusetts Burlington SGY Tel 781 238 0870 Michigan Byron Center R A Tel 616 554 1460 Good Rich R A Tel 810 636 6060...

Page 382: ...ton Mint Technology 77 South Bedford Street Burlington MA 01803 Tel 781 685 3800 Fax 781 685 3801 Minnesota Minneapolis 8300 Norman Center Drive Suite 730 Minneapolis MN 55437 Tel 612 921 8300 Fax 612...

Page 383: ...Singapore Singapore LSI Logic Pte Ltd 7 Temasek Boulevard 28 02 Suntec Tower One Singapore 038987 Tel 65 334 9061 Fax 65 334 4749 Sweden Stockholm LSI Logic AB Finlandsgatan 14 164 74 Kista Tel 46 8...

Page 384: ...ei Time24 Bldg 35 Tansu cho Shinjuku ku Tokyo 162 0833 Tel 81 3 3260 1411 Fax 81 3 3260 7100 Technical Center Tel 81 471 43 8200 Marubeni Solutions 1 26 20 Higashi Shibuya ku Tokyo 150 0001 Tel 81 3 5...

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