LSI LSI53C1000, Technical Manual

Page: 14 / 384

xiv Contents
6.11 Input Signals—CLK, GNT/, IDSEL, INT_DIR, RST/,
SCLK, TCK, TDI, TEST_HSC, TEST_RST/,
TEST_PD, TMS
6-6
6.12 8 mA Output Signals—INTA/, INTB/, ALT_INTA/,
ALT_INTB/, REQ/, SERR/
6-6
6.13 TolerANT Technology Electrical Characteristics for
SE SCSI Signals
6-7
6.14 External Clock 6-11
6.15 Reset Input 6-12
6.16 Interrupt Output 6-13
6.17 PCI Configuration Register Read 6-15
6.18 PCI Configuration Register Write 6-16
6.19 Operating Register/SCRIPTS RAM Read, 32 Bits 6-17
6.20 Operating Register/SCRIPTS RAM Read, 64 Bits 6-18
6.21 Operating Register/SCRIPTS RAM Read, 32 Bits 6-20
6.22 Operating Register/SCRIPTS RAM Write, 64 Bits 6-22
6.23 Nonburst Opcode Fetch, 32-Bit Address and Data 6-24
6.24 Burst Opcode Fetch, 32-Bit Address and Data 6-26
6.25 Back to Back Read, 32-Bit Address and Data 6-28
6.26 Back to Back Write, 32-Bit Address and Data 6-30
6.27 Burst Read, 32-Bit Address and Data 6-32
6.28 Burst Read, 64-Bit Address and Data 6-34
6.29 Burst Write, 32-Bit Address and Data 6-36
6.30 Burst Write, 64-Bit Address and Data 6-38
6.31 External Memory Read 6-41
6.32 External Memory Write 6-45
6.33 Normal/Fast Memory (
≥
128 Kbytes) Single Byte
Access Read Cycle 6-48
6.34 Normal/Fast Memory (
≥
128 Kbytes) Single Byte
Access Write Cycle 6-50
6.35 Slow Memory (
≥
128 Kbytes) Read Cycle 6-56
6.36 Slow Memory (
≥
128 Kbytes) Write Cycle 6-58
6.37
≤
64 Kbytes ROM Read Cycle 6-60
6.38
≤
64 Kbytes ROM Write Cycle 6-61
6.39 Initiator Asynchronous Send 6-62
6.40 Initiator Asynchronous Receive 6-63
6.41 Target Asynchronous Send 6-63
6.42 Target Asynchronous Receive 6-64