PCI and External Memory Interface Timing Diagrams
6-45
Table 6.32
External Memory Write
Symbol
Parameter
Min
Max
Min
Max
Unit
t
1
Shared signal input setup time
3
–
7
–
ns
t
2
Shared signal input hold time
0
–
0
–
ns
t
3
CLK to shared signal output valid
2
6
2
11
ns
t
11
Address setup to MAS/ HIGH
25
–
25
–
ns
t
12
Address hold from MAS/ HIGH
15
–
15
–
ns
t
13
MAS/ pulse width
25
–
25
–
ns
t
20
Data setup to MWE/ LOW
30
–
30
–
ns
t
21
Data hold from MWE/ HIGH
20
–
20
–
ns
t
22
MWE/ pulse width
100
–
100
–
ns
t
23
Address setup to MWE/ LOW
60
–
60
–
ns
t
24
MCE/ LOW to MWE/ HIGH
120
–
120
–
ns
t
25
MCE/ LOW to MWE/ LOW
25
–
25
–
ns
t
26
MWE/ HIGH to MCE/ HIGH
25
–
25
–
ns
Summary of Contents for LSI53C1000
Page 6: ...vi Preface...
Page 16: ...xvi Contents...
Page 28: ...1 12 Introduction...
Page 234: ...4 124 Registers...
Page 314: ...6 40 Specifications This page intentionally left blank...
Page 318: ...6 44 Specifications This page intentionally left blank...
Page 344: ...6 70 Specifications This page intentionally left blank...
Page 350: ...6 76 Specifications Figure 6 42 LSI53C1000 329 Ball Grid Array Bottom view...
Page 352: ...6 78 Specifications...
Page 360: ...A 8 Register Summary...
Page 376: ...IX 12 Index...