LSI LSI53C1000, Technical Manual

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SCSI Functional Description 2-39
2.2.12.4 Synchronous SCSI Receive
When a phase mismatch occurs during a synchronous SCSI receive
transfer no data recover operation is necessary. All data, including chain
bytes from Chained Block Moves, are flushed from the device prior to the
phase mismatch occurring. To recover from all other error conditions,
clear the DMA FIFO by setting bit 2 (CLF) in
Chip Test Three (CTEST3) ,
clear the SCSI FIFO by setting bit 1 (CSF) in SCSI Test Three (STEST3) ,
and retry the I/O.
2.2.13 SCSI Bus Interface
The LSI53C1000 performs SE and LVD transfers.
2.2.13.1 SCSI Bus Modes
To increase device connectivity and SCSI cable length, the LSI53C1000
features LVDlink technology, the LSI Logic implementation of LVD SCSI.
LVDlink transceivers provide the inherent reliability of differential SCSI
and a long-term migration path for faster SCSI transfer rates.
HVD is not supported by this device. Bit 2 of the SCSI Status Two
(SSTAT2) register and bit 5 of the SCSI Status Two (SSTAT2) register are
now reserved. The A_DIFFSENS or B_DIFFSENS signals still detect the
different input voltages for HVD, LVD, and SE, but the HVD feature is not
present.
2.2.13.2 SCSI Termination
The terminator networks pull signals to an inactive voltage level and
match the impedance seen at the end of the cable with the characteristic
impedance of the cable. Terminators must be installed at the extreme
ends of the SCSI chain, and only at the ends; no system should ever
have more or less than two terminators. SCSI host adapters should
provide a means of accommodating terminators. There should be a
means of disabling the termination.
SE cables can use a 220
Ω
pull-up resistor to the terminator power
supply (Term-Power) line and a 330
Ω
pull-down resistor to ground.
Because of the high-performance nature of the LSI53C1000, regulated