LSI LSI53C1000, Technical Manual, Page: 195 / 384

SCSI Registers 4-85
R Reserved [5:4]
SZM SCSI High Impedance Mode 3
Setting this bit places all the open drain 48 mA SCSI
drivers into a high impedance state.
R Reserved [2:1]
LOW SCSI Low Level Mode 0
Setting this bit places the LSI53C1000 in the low level
mode. In this mode, no DMA operations occur and no
SCRIPTS execute. Arbitration and selection may be
performed by setting the start sequence bit as described
in the
SCSI Control Zero (SCNTL0) register. SCSI bus
transfers are performed by manually asserting and polling
SCSI signals. Clearing this bit allows instructions to be
executed in the SCSI SCRIPTS mode.
Note: It is not necessary to set this bit for access to the SCSI
bit-level registers (
SCSI Output Data Latch (SODL) , SCSI
Bus Control Lines (SBCL) , and input registers).
Register: 0x4F
SCSI Test Three (STEST3)
Read/Write
TE TolerANT Enable 7
Setting this bit enables the active negation portion of
LSI Logic TolerANT technology. Active negation causes
the SCSI Request, Acknowledge, Data, and Parity
signals to be actively deasserted, instead of relying on
external pull-ups, when the LSI53C1000 is driving these
signals. Active deassertion of these signals occurs only
when the LSI53C1000 is in an information transfer phase.
When performing synchronous transfers, TolerANT
should be enabled to improve setup and deassertion
times. Active negation is disabled after reset or when this
bit is cleared. For more information on LSI Logic
TolerANT technology, see
Chapter 1, “Introduction.”
7 6 5 4 3 2 1 0
TE R HSC DSI R TTM CSF R
0 0 0 0 0 0 0 0