LSI LSI53C1000, Technical Manual

Page: 226 / 384

4-116 Registers
Register: 0xE3
CRC Control One (CRCCNTL1)
Read/Write
CRCERR CRC Error 7
This bit indicates whether or not a CRC error has been
detected during a DT Data-In SCSI transfer. This bit is set
independent of the DCRCC bit. To clear this condition,
either write this bit to a 1 or read the SIST0 and SIST1
registers. When CRC Checking and the Parity/CRC/AIP
Error Interrupt are enabled, this error condition is also
indicated as a Parity/CRC/AIP error (bit 0 of the SIST0
register).
R Reserved 6
ENAS Enable CRC Auto Seed 5
Setting this bit causes the CRC logic to automatically
reseed after every CRC check performed during DT
Data-In SCSI transfers. When this bit is cleared, the SCSI
control logic controls when the reseeding occurs.
TSTSD Test CRC Seed 4
Setting this bit causes the CRC logic to immediately
reseed itself. This bit should never be set during normal
operation as it may cause corrupt CRCs to be generated.
TSTCHK Test CRC Check 3
Setting this bit causes the CRC logic to initiate a CRC
check. This bit should never be set during normal
operation as it results in spurious CRC errors.
TSTADD Test CRC Accumulate 2
Setting this bit causes the CRC block to take the value in
its input register and add it into the current CRC
calculation, resulting in a new output CRC value. This bit
should not be set during normal operation as it results in
corrupt CRC values.
7 6 5 4 3 2 1 0
CRCERR R ENAS TSTSD TSTCHK TSTADD CRCDSEL
0 0 0 0 0 0 0 0