LSI LSI53C1000, Technical Manual

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2-62 Functional Description
2.4.2 No Download Mode
When MAD[7] is pulled up through an external resistor, the automatic
download is disabled and data is not automatically loaded into chip
registers at power-up. The Subsystem ID and Subsystem Vendor ID
registers are read only, per the PCI specification, with a default value of
0x1000 and 0x1000 respectively.
2.5 Power Management
The LSI53C1000 complies with the PCI Bus Power Management
Interface Specification, Revision 1.1, in which the D0, D1, D2, and D3
are defined.
D0 is the maximum powered state, and D3 is the minimum powered
state. Power state D3 is further categorized as D3hot or D3cold. A device
that is powered off is in the D3cold power state.
The LSI53C1000 power states are independently controlled through two
power state bits that are located in the PCI Configuration Space
Power
Management Control/Status (PMCSR) register, 0x44–0x45 . The power
state bit settings are provided in Table 2.9 .
0xFD SID(0) Subsystem ID (SID) , LSB. This byte is loaded into the
least significant byte of the Subsystem ID register in the
appropriate PCI configuration space at chip power-up.
0xFE SID(1) Subsystem ID (SID) , MSB. This byte is loaded into the
most significant byte of the Subsystem ID register in the
appropriate PCI configuration space at chip power-up.
0xFF CKSUM Checksum (CKSUM). This 8-bit checksum is formed by
adding, bytewise, each byte contained in locations
0xFB–0xFE to the seed value (0x55) and then taking the
2’s complement of the result.
Table 2.8 Default Download Mode Serial EEPROM Data Format
(Cont.)
Byte Name Description