PCI Bus Interface Signals
3-7
3.3.3 Interface Control Signals
describes the Interface Control Signals group.
Table 3.4
Interface Control Signals
Name
Bump
Type
Strength
Description
ACK64/
AB1
S/T/S 8 mA PCI Acknowledge 64-bit transfer is driven by the current bus
target to indicate its ability to transfer 64-bit data.
REQ64/
AA2
S/T/S 8 mA PCI Request 64-bit transfer is driven by the current bus master
to indicate a request to transfer 64-bit data.
FRAME/
P2
S/T/S 8 mA PCI Cycle Frame is driven by the current master to indicate the
beginning and duration of an access. FRAME/ is asserted
to indicate that a bus transaction is beginning. While
FRAME/ is deasserted, either the transaction is in the final
data phase or the bus is idle.
TRDY/
P3
S/T/S 8 mA PCI Target Ready indicates the target’s ability to complete the
current data phase of the transaction. TRDY/ is used with
IRDY/. A data phase is completed on any clock when both
TRDY/ and IRDY/ are sampled asserted. During a read,
TRDY/ indicates that valid data is present on the AD bus.
During a write, it indicates that the target is prepared to
accept data.
IRDY/
N4
S/T/S 8 mA PCI Initiator Ready indicates the initiator’s ability to complete
the current data phase of the transaction. IRDY/ is used with
TRDY/. A data phase is completed on any clock when both
IRDY/ and TRDY/ are sampled asserted. During a write,
IRDY/ indicates that valid data is present on the AD bus.
During a read, it indicates that the master is prepared to
accept data.
STOP/
R2
S/T/S 8 mA PCI Stop indicates that the selected target is requesting the
master to stop the current transaction.
DEVSEL/
R1
S/T/S 8 mA PCI Device Select indicates that the driving device has
decoded its address as the target of the current access. As
an input, it indicates to a master whether any device on the
bus has been selected.
IDSEL
L3
I
N/A
Initialization Device Select is used as a chip select, in
place of the upper 24 address lines, during configuration
read and write transactions.
Summary of Contents for LSI53C1000
Page 6: ...vi Preface...
Page 16: ...xvi Contents...
Page 28: ...1 12 Introduction...
Page 234: ...4 124 Registers...
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Page 318: ...6 44 Specifications This page intentionally left blank...
Page 344: ...6 70 Specifications This page intentionally left blank...
Page 350: ...6 76 Specifications Figure 6 42 LSI53C1000 329 Ball Grid Array Bottom view...
Page 352: ...6 78 Specifications...
Page 360: ...A 8 Register Summary...
Page 376: ...IX 12 Index...