LSI LSI53C1000, Technical Manual

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SCSI Functional Description 2-33
any external PCI slave cycles that occur are retried on the PCI bus.
Setting the DISRC (Disable Internal SCRIPTS RAM Cycles) bit in the
Chip Control Zero (CCNTL0) register disables this feature. For more
information on the Load and Store instructions, refer to Chapter 5, “SCSI
SCRIPTS Instruction Set.”
2.2.9 JTAG Boundary Scan Testing
With one exception, the LSI53C1000 includes support for JTAG
boundary scan testing in accordance with the IEEE 1149.1 specification.
The exception concerns the TST_RSTN pin. This pin must not be
toggled as it will reset the JTAG TAP controller. For more information,
refer to the BSDL (Boundary Scan Descriptor Language) file.
This device accepts all required boundary scan instructions including the
optional CLAMP, HIGH-Z, and IDCODE instructions. The optional JTAG
pin TRST is not implemented. Reset of the JTAG logic through the TAP
controller occurs when TMS is held high for at least 5 TCK clock cycles.
The LSI53C1000 uses an 8-bit instruction register to support all
boundary scan instructions. The data registers included in the device are
the Boundary Data register, the IDCODE register, and the Bypass
register. This device can handle a 20 MHz TCK frequency with all TAP
pins having a 50% duty cycle.
2.2.10 Parity/CRC/AIP Options
The LSI53C1000 implements a flexible parity scheme that permits
control of the parity sense, allows parity checking to be turned on or off,
and can deliberately send a byte with bad parity over the SCSI bus.
Table 2.4 defines the bits that are involved in parity control and
observation. Table 2.5 describes the parity control function of the Enable
Parity Checking and Assert SCSI Even Parity bits in the SCSI Control
One (SCNTL1) register, bit 2, and the options available when a parity
error occurs.
SCRIPTS RAM must first be written before being read in order to
initialize SCRIPTS RAM parity. If a SCRIPTS RAM parity error is
encountered, a SCSI Gross Error interrupt is signaled.
The LSI53C1000 supports CRC checking and generation in DT phases
and CRC checking and generation during DT Data Transfers.