xr
PRELIMINARY
XRT86VL38
REV. P1.0.6
OCTAL T1/E1/J1 FRAMER/LIU COMBO
46
WR
M23
L20
I
Microprocessor Interface—Write Strobe Input
The exact behavior of this pin depends upon the type of Micropro-
cessor/Microcontroller the XRT86VL38 has been configured to oper-
ate in, as defined by the PTYPE[2:0] pins.
Intel-Asynchronous Mode - WR* - Write Strobe Input:
If the Microprocessor Interface is configured to operate in the Intel-
Asynchronous Mode, then this input pin functions as the WR*
(Active Low WRITE Strobe) input signal from the Microprocessor.
Once this active-low signal is asserted, then the input buffers (asso-
ciated with the Bi-Directional Data Bus pin, D[7:0]) will be enabled.
The Microprocessor Interface will latch the contents on the Bi-Direc-
tional Data Bus (into the “target” register or address location, within
the XRT86VL38) upon the rising edge of this input pin.
Motorola-Asynchronous Mode - R/W* - Read/Write Operation
Identification Input Pin:
If the Microprocessor Interface is operating in the “Motorola-Asyn-
chronous Mode”, then this pin is functionally equivalent to the “R/
W*” input pin. In the Motorola Mode, a “READ” operation occurs if
this pin is held at a logic “1”, coincident to a falling edge of the RD/
DS* (Data Strobe) input pin. Similarly a WRITE operation occurs if
this pin is at a logic “0”, coincident to a falling edge of the RD/DS*
(Data Strobe) input pin.
Power PC 403 Mode - R/W* - Read/Write Operation Identifica-
tion Input:
If the Microprocessor Interface is configured to operate in the Power
PC 403 Mode, then this input pin will function as the “Read/Write
Operation Identification Input” pin.
Anytime the Microprocessor Interface samples this input signal at a
logic low (while also sampling the CS* input pin “low”) upon the ris-
ing edge of PCLK, then the Microprocessor Interface will (upon the
very same rising edge of PCLK) latch the contents of the Address
Bus (A[14:0]) into the Microprocessor Interface circuitry, in prepara-
tion for this forthcoming READ operation. At some point (later in this
READ operation) the Microprocessor will also assert the DBEN*/
OE* input pin, and the Microprocessor Interface will then place the
contents of the “target” register (or address location within the
XRT86VL38 device) upon the Bi-Directional Data Bus pins (D[7:0]),
where it can be read by the Microprocessor .
Anytime the Microprocessor Interface samples this input signal at a
logic high (while also sampling the CS* input pin a logic “low”) upon
the rising edge of PCLK, then the Microprocessor Interface will
(upon the very same rising edge of PCLK) latch the contents of the
Address Bus (A[14:0]) into the Microprocessor Interface circuitry, in
preparation for the forthcoming WRITE operation. At some point
(later in this WRITE operation) the Microprocessor will also assert
the RD*/DS*/WE* input pin, and the Microprocessor Interface will
then latch the contents of the Bi-Directional Data Bus (D[7:0]) into
the contents of the “target” register or buffer location (within the
XRT86VL38).
MICROPROCESSOR INTERFACE
S
IGNAL
N
AME
420 P
KG
B
ALL
#
484P
KG
B
ALL
#
T
YPE
D
ESCRIPTION
