xr
PRELIMINARY
XRT86VL38
REV. P1.0.6
OCTAL T1/E1/J1 FRAMER/LIU COMBO
38
T1MCLKnOUT
D6
F9
O
LIU T1 Output Clock Reference
This output pin is defaulted to 1.544MHz, but can be programmed
to output 3.088MHz, 6.176MHz, or 12.352MHz in register 0x0FE4.
E1OSCCLK
Y5
V4
O
Framer E1 Output Clock Reference
This output pin is defaulted to 2.048MHz, but can be programmed
to 65.536MHz in register 0x011E.
T1OSCCLK
AC1
V3
O
Framer T1 Output Clock Reference
This output pin is defaulted to 1.544MHz, but can be programmed
to output 49.408MHz in register 0x011E.
8KSYNC
AB3
W2
O
8kHz Clock Output Reference
This pin is an output reference of 8kHz based on the MCLKIN input.
Therefore, the duty cycle of this output is determined by the time
period of the input clock reference.
8KEXTOSC
AA2
U5
I
External Oscillator Select
For normal operation, this pin should not be used, or pulled “Low”.
This pin is internally pulled “Low” with a 50k
Ω
resistor.
ANALOG
C5
D4
O
Factory Test Mode Pin
N
OTE
: For Internal Use Only
LOP
AB1
V2
I
Loss of Power for E1 Only / Input Pin for Messaging
This is a Loss of Power pin in the E1 application only. Upon detect-
ing LOP in E1 mode, the device will automatically transmit the Sa5
and Sa6 bit to a different pattern, so that the Receive terminal can
detect a power failure in the network.
Please see register 0xn131 for the Transmit SA control.
SENSE
E6
E6
O
N
OTE
: For Internal Use Only
TIMING INTERFACE
S
IGNAL
N
AME
420 P
KG
B
ALL
#
484 P
KG
B
ALL
#
T
YPE
D
ESCRIPTION