xr
PRELIMINARY
XRT86VL38
REV. P1.0.6
OCTAL T1/E1/J1 FRAMER/LIU COMBO
66
3.3.3
DMA Read/Write Operations
The XRT86VL38 Framer contains two DMA Controller Interfaces which provide support for all four framers
within the chip. The purpose of the two DMA Controllers is to facilitate the rapid block transfer of data between
an external memory location and the on-chip HDLC buffers via the Microprocessor Interface.
DMA-0 Write DMA Interface
DMA 0 Controller Interface handles data transfer between external memory and the selected Transmit HDLC
Buffer.
The DMA cycle starts when the XRT86VL38 asserts the REQ0 output pin. The external DMA Controller then
responds by asserting the ACK0 input pin. The contents of the Microprocessor Interface bi-directional data bus
are latched into the XRT86VL38 each time the WR (Write Strobe) input pin is strobed “Low”.
The XRT86VL38 ends the DMA cycle by negating the DMA request input (REQ0) while WR is still active. The
external DMA Controller acknowledges the end of DMA Transfer by driving the ACK0 input pin “High”.
F
IGURE
10. P
OWER
PC M
ODE
I
NTERFACE
S
IGNALS
D
URING
W
RITE
O
PERATIONS
PCLK
CS*
R/W*
A[14:0]
D[7:0]
WE*
OE*
RDY
Target Address
Data to be Written
Microprocessor places “target”
Address on A[14:0]
Microprocessor sets R/W*
To logic “Low” to denote
WRITE Operation
Microprocessor asserts WE* (RD*/DS*)
Here to initiate WRITE Operation
XRT86VL38 responds by latching the
Contents of the Data Bus (into the
“target” address location), and by
Asserting RDY
WRITE Operation
Is terminated
Here
XRT86VL38 samples
A[14:0] here
XRT86VL38 samples
WE* Here