XRT86VL38
PRELIMINARY
xr
OCTAL T1/E1/J1 FRAMER/LIU COMBO
REV. P1.0.6
349
7.3.3
Transmit Jitter Attenuator
The transmit path has a dedicated jitter attenuator to reduce phase and frequency jitter in the transmit clock.
The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth of 32-bit or 64-bit. When
the Read and Write pointers of the FIFO are within 2-Bits of over-flowing or under-flowing, the bandwidth of the
jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this
condition occurs, the jitter attenuator will not attenuate input jitter until the Read/Write pointer’s position is
outside the 2-Bit window. In T1 mode, the bandwidth of the JA is always set to 3Hz. In E1 mode, the
bandwidth is programmable to either 10Hz or 1.5Hz (1.5Hz automatically selects the 64-Bit FIFO depth). The
JA has a clock delay equal to ½ of the FIFO bit depth.
N
OTE
: The Receive Path has a dedicated jitter attenuator. See the Receive Path Line Interface Section.
