xr
PRELIMINARY
XRT86VL38
REV. P1.0.6
OCTAL T1/E1/J1 FRAMER/LIU COMBO
58
3.2.1
The Motorola-Asynchronous Read-Cycle
If the Microprocessor Interface has been configured to operate in the Motorola-Asynchronous Mode, then the
Microprocessor should do all of the following to perform a read operation:
1.
Place the address of the "target" register within the XRT86VL38 device, on the Address Bus Input pins,
A[14:0].
2.
While the microprocessor is placing the address value on the Address Bus, the Address Decoding circuitry
(within the user's system) should assert the CS* (Chip Select) pin of the XRT86VL38 device, by toggling it
"low". This action enables further communication between the microprocessor and the XRT86VL38 Micro-
processor Interface block.
T
ABLE
6: T
HE
R
OLES
OF
V
ARIOUS
M
ICROPROCESSOR
I
NTERFACE
P
INS
,
WHEN
CONFIGURED
TO
OPERATE
IN
THE
M
OTOROLA
-A
SYNCHRONOUS
M
ODE
P
IN
N
AME
420 P
KG
B
ALL
#
484 P
KG
B
ALL
#
T
YPE
D
ESCRIPTION
ALE/AS*
R22
P22
I
Address Latch Enable Input - ALE
If the Microprocessor Interface has been configured to operate in the Motorola-
Asynchronous Mode, then this active-low input pin is used to latch the data
(residing on the Address Bus, A[14:0]) into the Microprocessor Interface circuitry
of the XRT86VL38 device.Pulling this input pin "low" enables the input bus driv-
ers for the Address Bus input pins. The contents of the Address Bus will be
latched into the Microprocessor Interface circuitry, upon the rising edge of this
input signal.
RD*/DS*/
WE*
W25
U21
I
Data Strobe Input - DS*
If the Microprocessor Interface is operating in the Motorola-Asynchronous Mode,
then this input pin will function as the DS* (Data Strobe) input signal.
RDY*/
DTACK*/
RDY
V24
R19
O
Active Low Ready Output - RDY*
If the Microprocessor Interface has been configured to operate in the Motorola-
Asynchronous Mode, then this output pin will function as the "active-low" DTACK
output.During a READ or WRITE cycle, the Microprocessor Interface block will
toggle this output pin to the logic low level, ONLY when it (the Microprocessor
Interface) is ready to complete or terminate the current READ or WRITE cycle.
Once the Microprocessor has determined that this input pin has toggled to the
logic "low" level, then it is now safe for it to move on and execute the next READ
or WRITE cycle. If (during a READ or WRITE cycle) the Microprocessor Inter-
face block is holding this output pin at a logic "high" level, then the Microproces-
sor is expected to extend this READ or WRITE cycle, until it detects this output
pin being toggled to the logic low level.
PCLK
Y25
V22
I
NONE - Tie to GND
WR*/R/
W*
M23
L20
I
Write Strobe Input - WR*
If the Microprocessor Interface is operating in the "Motorola-Asynchronous
Mode", then this pin is functionally equivalent to the "R/W*" input pin. In the
Motorola Mode, a "READ" operation occurs if this pin is held at a logic "1", coin-
cident to a falling edge of the RD/DS* (Data Strobe) input pin. Similarly a
WRITE operation occurs if this pin is at a logic "0", coincident to a falling edge of
the RD/DS* (Data Strobe) input pin.
DBEN*
V23
U22
I
Data Bus Enable Input:
For Motorola-Asynchronous Mode operation, the user should either tie this pin to
a logic "low" or assert this pin (e.g., toggle it to a logic "low") when performing a
READ operation with the Microprocessor Interface of the XRT86VL38 device.
BLAST
P23
M17
I
NONE - Tie this pin to GND
