ABB Relion RES670, Technical Manual

Page: 484 / 934

Figure 187 describes the simplified logic of the function where the block “Time
Integration“ covers the logics for the first two items listed above while the block
“Transgression Supervision Plus Retain“ contains the logics for the last two.
Time Integration
Transgression Supervision
Plus Retain
BLOCK
ACCTIME RESET
IN
tAlarm
OVERFLOW
WARNING
ALARM
IEC12000195-4-en.vsd
Loop Delay
Loop Delay
tWarning
IEC12000195 V4 EN-US
Figure 187: TEIGAPC Simplified logic
TEIGAPC main functionalities
• integration of the elapsed time when IN has been high
•
applicable to long time integration (≤999 999.9 seconds)
• output
ACCTIME
presents integrated value in seconds
• integrated value is retained in nonvolatile memory
• any retained value with a warning/alarm/overflow is used as initiation value
for the integration following by a restart
•
RESET
: Reset of the integration value. Consequently all other outputs are also
reset
•
unconditionally on the input
IN
value
• reset the value of the nonvolatile memory to zero
•
BLOCK
: Freeze the integration and block/reset the other outputs
• unconditionally on the signal value
•
BLOCK
request overrides
RESET
request
• Monitor and report the conditions of limit transgression
Section 15
1MRK 511 408-UUS A
Logic
478 Phasor measurement unit RES670 2.2 ANSI
Technical manual