Xilinx Virtex-II Pro PPC405, User Manual

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March 2002 Release www.xilinx.com 385
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Integer Load and Store Instructions
R
Store Word
Table 3-20 lists the PowerPC store word instructions. These instructions store the entire
contents of r S into the specified word location in memory.
Load and Store with Byte-Reverse Instructions
Table 3-21 lists the PowerPC load and store with byte-reverse instructions. Figure 3-20 shows
(using big-endian memory) how bytes are moved between memory and the GPRs for each
of the byte-reverse instructions. When an
lhbrx instruction is executed, the unloaded bytes
in r D are cleared to 0.
When used in a system operating with the default big-endian byte order, these instructions
have the effect of loading and storing data in little-endian order. Likewise, when used in a
system operating with little-endian byte order, these instructions have the effect of loading
Table 3-19: Store Halfword Instructions
Mnemonic Name Addressing Mode
Operand
Syntax
sth Store Halfword Register-indirect with immediate index
EA
=
( r A|0)
+
d
r S,d( r A)
sthu Store Halfword with Update Register-indirect with immediate index
EA
=
( r A)
+
d
r A
←
EA
r A
≠
0
sthx Store Halfword Indexed Register-indirect with index
EA
=
( r A|0)
+
( r B)
r S, r A, r B
sthux Store Halfword with Update Indexed Register-indirect with index
EA
=
( r A)
+
( r B)
r A
←
EA
r A
≠
0
Table 3-20:
Store Word Instructions
Mnemonic Name Addressing Mode
Operand
Syntax
stw Store Word Register-indirect with immediate index
EA
=
( r A|0)
+
d
r S,d( r A)
stwu Store Word with Update Register-indirect with immediate index
EA
=
( r A)
+
d
r A
←
EA
r A
≠
0
stwx Store Word Indexed Register-indirect with index
EA
=
( r A|0)
+
( r B)
r S, r A, r B
stwux Store Word with Update Indexed Register-indirect with index
EA
=
( r A)
+
( r B)
r A
←
EA
r A
≠
0