March 2002 Release
561
Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
R
Chapter 10
Reset and Initialization
This chapter describes the reset operations recognized by the PPC405, the initial state of the
PPC405 after a reset, and an example of the initialization code required to configure the
processor. Initialization of external devices (on-chip or off-chip) is outside the scope of this
document.
Reset
A
reset
causes the processor to perform a hardware initialization. It always occurs when the
processor is powered-up and can occur at any time during normal operation. If it occurs
during normal operation, instruction execution is immediately halted and all processor
state is lost.
The PPC405 recognizes three types of reset:
•
A
processor reset
affects the processor only, including the execution units and cache
units. External devices (on-chip and off-chip) are not affected. This type of reset is
sometimes referred to as a core reset.
•
A
chip reset
affects the processor and all other devices or peripherals located on the
same chip as the processor.
•
A
system reset
affects the processor chip and all other devices or peripherals external to
the processor chip that are connected to the same system-reset network. The scope of
a system reset depends on the system implementation.
The type of reset is recorded in the most-recent reset field of the debug-status register
(DBSR[MRR]). System software can examine this field if it needs to determine the cause of
a reset. The effect of a reset on the processor is always the same regardless of the type.
Reset is caused by any of the following conditions:
•
The processor is powered-up. Normally, the system performs a power-up sequence
that includes asserting the external reset signals during a system reset.
•
During normal operation, a system reset can be asserted using external reset signals.
The processor logs this as a system reset, never as a processor reset or a chip reset.
•
The second time-out of the watchdog timer can be programmed to cause a reset.
•
Software can cause a reset by writing a non-zero value into the reset field of debug-
control register 0 (DBCR0[RST]).
•
An external debug tool can force a reset through the JTAG debug port.
Throughout this document, the term “reset” is applied collectively to all forms of reset. A
type of reset is specified explicitly only when it is germane to the discussion.
Processor State After Reset
System software is responsible for fully initializing and configuring most processor
resources. After a reset, the contents of most PPC405 registers are undefined and software
