March 2002 Release
711
Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
Alphabetical Instruction Listing
R
rfi
Return from Interrupt
Description
This is a privileged instruction.
The MSR is loaded with the contents of SRR1. The contents of SRR0 are used as the next-
instruction address (NIA). Program control is transferred to the NIA. This instruction is
context synchronizing. Instructions fetched from the NIA use the new context loaded into
the MSR.
Pseudocode
(MSR
) ←
(SRR1)
Synchronize context
NIA
←
(SRR0)
Registers Altered
•
MSR.
Exceptions
•
Program—Attempted execution of this instruction from user mode.
Execution of any of the following invalid-instruction forms results in a boundedly-
undefined result rather than a program exception:
•
Reserved bits containing a non-zero value.
Compatibility
This instruction is defined by the operating-environment architecture level (OEA) of the
PowerPC architecture, the PowerPC embedded-environment architecture, and the
PowerPC Book-E architecture. It is implemented by all PowerPC processors.
rfi
XL Instruction Form
19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
50
0
0
6
2
1
3
1
