Xilinx Virtex-II Pro PPC405, User Manual

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March 2002 Release www.xilinx.com 421
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Multiply-Accumulate Instruction-Set Extensions
R
Figure 3-35 shows the operation of the multiply high-halfword to word instructions.
Multiply Low-Halfword to Word Instructions
Table 3-48 shows the PPC405 multiply low-halfword to word instructions. These instructions
multiply the low halfword of both source operands, r A[16:31] and r B[16:31], producing a
32-bit product. The product is signed or unsigned, depending on the instruction.
For each type of instruction shown in Table 3-48 , the “Operation” column indicates the
multiply operation performed. The column also shows, on an instruction-by-instruction
basis, how the CR register is updated (if at all). The XER register is not updated by these
instructions.
Multiply High-Halfword to Word Unsigned
Instructions
r D is loaded with the unsigned product ( r A[0:15])
×
( r B[0:15]).
mulhhwu Multiply High Halfword to Word
Unsigned
CR0 is
not
updated.
r D, r A, r B
mulhhwu. Multiply High Halfword to Word
Unsigned and Record
CR0 is updated to reflect the result.
Table 3-47: Multiply High-Halfword to Word Instructions (Continued)
Mnemonic Name Operation
Operand
Syntax
Figure 3-35: Multiply High-Halfword to Word Operation
UG011_27_033101
r D
0 31
r A
0 31 16
r B
0 31 15
×
Table 3-48:
Multiply Low-Halfword to Word Instructions
Mnemonic Name Operation
Operand
Syntax
Multiply Low-Halfword to Word Signed Instructions
r D is loaded with the signed product ( r A[16:31])
×
( r B[16:31]).
mullhw
Multiply Low Halfword to Word
Signed
CR0 is
not
updated.
r
D,
r
A,
r
B
mullhw. Multiply Low Halfword to Word
Signed and Record
CR0 is updated to reflect the result.