Xilinx Virtex-II Pro PPC405, User Manual

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458 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 5: Memory-System Management
R
Table 5-5: Data-Cache Control Instructions
Mnemonic Name Operation
Operand
Syntax
dcba Data Cache Block Allocate An effective address (EA) is calculated using
register-indirect with index addressing:
EA
=
( r A|0)
+
( r B)
This instruction can be used as a hint that a
program might soon store into EA. It allocates a
data cacheline for the byte addressed by EA. A
subsequent store to EA hits the cache, improving
program performance.
r A, r B
dcbf Data Cache Block Flush If the byte specified by the effective address (EA) is
cached by the data cache, the cacheline containing
that byte is invalidated. If the cacheline is modified
(dirty), the entire contents of the cacheline are
written to system memory before the line is
invalidated.
EA is calculated using register-indirect with index
addressing:
EA
=
( r A|0)
+
( r B)
r A, r B
dcbi Data Cache Block Invalidate If the byte specified by the effective address (EA) is
cached by the data cache, the cacheline containing
that byte is invalidated. If the cacheline is modified
(dirty), those modifications are lost.
EA is calculated using register-indirect with index
addressing:
EA
=
( r A|0)
+
( r B)
r A, r B
dcbst Data Cache Block Store If the byte specified by the effective address (EA) is
cached by the data cache and the cacheline is
modified (dirty), the entire contents of the
cacheline are written to system memory. After the
store completes, the cacheline is marked as
unmodified (not dirty).
EA is calculated using register-indirect with index
addressing:
EA
=
( r A|0)
+
( r B)
r A, r B
dcbt Data Cache Block Touch If the byte specified by the effective address (EA) is
cacheable and is not currently cached by the data
cache, the cacheline containing that byte is loaded
into the data cache from system memory.
EA is calculated using register-indirect with index
addressing:
EA
=
( r A|0)
+
( r B)
r A, r B
dcbtst Data Cache Block Touch for Store If the byte specified by the effective address (EA) is
cacheable and is not currently cached by the data
cache, the cacheline containing that byte is loaded
into the data cache from system memory.
EA is calculated using register-indirect with index
addressing:
EA
=
( r A|0)
+
( r B)
r A, r B