Xilinx Virtex-II Pro PPC405, User Manual

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704 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 11: Instruction Set
R
nmaclhws
Negative Multiply Accumulate Low Halfword to Word Saturate Signed
Description
The low-order halfword of r A is multiplied by the low-order halfword of r B. The negated
signed product is added to the contents of r D and the sum is stored as a 33-bit temporary
result.
If the result does not overflow, the low-order 32 bits of the temporary result are stored in
r D. If the result overflows, r D is loaded with the nearest representable value. If the result is
less than
−
2
31
, the value stored in r D is
−
2
31
. If the result is greater than 2
31
−
1, the value
stored in r D is 2
31
−
1. An example of this operation is shown in Figure 3-33, page 419 .
Pseudocode
prod
0:31
←
( r A)
16:31
×
( r B)
16:31
signed
nprod
0:31
←
−
1
×
prod
0:31
signed
temp
0:32
←
nprod
0:31
+ ( r D)
if ((nprod
0
=
r D
0
)
∧
( r D
0
≠
temp
1
))
then ( r D)
←
( r D
0
||
31
(
¬
r D
0
))
else ( r D)
←
temp
1:32
Registers Altered
• r D.
• CR[CR0]
LT, GT, EQ, SO
if Rc
=
1.
• XER[SO, OV] if OE
=
1
Exceptions
• None.
Compatibility
This instruction is implementation specific and is not guaranteed to be supported by other
PowerPC processors.
nmaclhws r D, r A, r B (OE=0, Rc=0)
nmaclhws. r D, r A, r B (OE=0, Rc=1)
nmaclhwso r D, r A, r B (OE=1, Rc=0)
nmaclhwso. r D, r A, r B (OE=1, Rc=1)
XO Instruction Form
4 r D r A r B OE 494 Rc
0 6 1
1 1
6 2
1 2
2 3
1