March 2002 Release
841
Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
Multiple-Precision Shifts
R
immediate shifts). The examples shown for
n
>
2 use
n
=
3. Extending those examples to
larger values of
n
or reducing them to the case
n
=
2 is straightforward when the shift
amount restriction is met. This restriction is always met for shifts with immediate shift
amounts.
The examples assume GPRs
r
2 and
r
3 (and
r
4 if
n
=
3) contain the quantity to be shifted and
that the result is placed into the same registers. For non-immediate shifts, the shift amount
is contained in bits 27:31 of GPR
r
6. For immediate shifts, the shift amount is assumed to be
greater than zero. GPRs
r
0 and
r
31 are used as scratch registers. The variable
sh
represents
the shift amount.
•
Shift-left immediate,
n
=
3 (shift amount
<
32)
rlwinm r
2,
r
2, sh, 0, 31
−
sh
rlwimi r
2,
r
3, sh, 32
−
sh, 31
rlwinm r
3,
r
3, sh, 0, 31
−
sh
rlwimi r
3,
r
4, sh, 32
−
sh, 31
rlwinm r
4,
r
4, sh, 0, 31
−
sh
•
Shift-left,
n
=
2 (shift amount
<
64)
subfic r
31,
r
6, 32
slw
r
2,
r
2,
r
6
srw
r
0,
r
3,
r
31
or
r
2,
r
2,
r
0
addi
r
31,
r
6,
−
32
slw
r
0,
r
3,
r
31
or
r
2,
r
2,
r
0
slw
r
3,
r
3,
r
6
•
Shift-left,
n
=
3 (shift amount
<
32)
subfic r
31,
r
6, 32
slw
r
2,
r
2,
r
6
srw
r
0,
r
3,
r
31
or
r
2,
r
2,
r
0
slw
r
3,
r
3,
r
6
srw
r
0,
r
4,
r
31
or
r
3,
r
3,
r
0
slw
r
4,
r
4,
r
6
•
Shift-right immediate,
n
=
3 (shift amount
<
32)
rlwinm r
4,
r
4, 32
−
sh, sh, 31
rlwimi r
4,
r
3, 32
−
sh, 0, sh
−
1
rlwinm r
3,
r
3, 32
−
sh, sh, 31
rlwimi r
3,
r
2, 32
−
sh, 0, sh
−
1
rlwinm r
2,
r
2, 32
−
sh, sh, 31
•
Shift-right,
n
=
2 (shift amount
<
64)
subfic r
31,
r
6, 32
srw
r
3,
r
3,
r
6
slw
r
0,
r
2,
r
31
or
r
3,
r
3,
r
0
addi
r
31,
r
6,
−
32
srw
r
0,
r
2,
r
31
or
r
3,
r
3,
r
0
srw
r
2,
r
2,
r
6
•
Shift-right,
n
=
3 (shift amount
<
32)
subfic r
31,
r
6,
−
32
srw
r
4,
r
4,
r
6
slw
r
0,
r
3,
r
31
or
r
4,
r
4,
r
0
srw
r
3,
r
3,
r
6
slw
r
0,
r
2,
r
31
or
r
3,
r
3,
r
0
srw
r
2,
r
2,
r
6
•
Shift-right algebraic immediate,
n
=
3 (shift amount
<
32)
