Xilinx Virtex-II Pro PPC405, User Manual

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792 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Appendix B: Instruction Summary
R
Instructions Grouped by Form
Table B-23 though Table B-31 list the PPC405 instruction set grouped by form. Within each
table, instructions are sorted in numeric order by primary and secondary opcode.
Table B-21: Cache Management Instructions
0 6 11 16 21 31
dcba 31 00000 r A r B 758 0
dcbf 31 00000 r A r B 86 0
dcbi 31 00000 r A r B 470 0
dcbst 31 00000 r A r B 54 0
dcbt 31 00000 r A r B 278 0
dcbtst 31 00000 r A r B 246 0
dcbz 31 00000 r A r B 1014 0
dccci 31 00000 r A r B 454 0
dcread 31 r D r A r B 486 0
icbi 31 00000 r A r B 982 0
icbt 31 00000 r A r B 262 0
iccci 31 00000 r A r B 966 0
icread 31 00000 r A r B 998 0
Table B-22: TLB Management Instructions
0
6 11 16 21 31
tlbia 31 00000 00000 00000 370 0
tlbre 31 r D r A WS 946 0
tlbsx 31 r D r A r B 914 Rc
tlbsync 31 00000 00000 00000 566 0
tlbwe 31 r S r A WS 978 0
Table B-23: B Form
0 6 11 16 30 31
bc 16 BO BI BD AA LK
Table B-24: D Form
0
6 9 11 16 31
twi 3 TO rA SIMM
mulli 7 rD rA SIMM
subfic 8 r D r A SIMM
cmpli 10 crf D 00 r A SIMM