Xilinx Virtex-II Pro PPC405, User Manual

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552 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
R
a read-access match is detected, the corresponding status bits in the DBSR are
set (DR1 and/or DR2). Likewise, write-access for the entire range is checked
by setting the D1W and/or D2W bits in the DBCR1 register. If a write-access
match is detected, the corresponding status bits in the DBSR are set (DW1
and/or DW2).
Inclusive and Exclusive Ranges
The DBCR1[DA12X] bit determines whether the address range specified by
the DAC
n registers is inclusive or exclusive:
• When DBCR1[DA12X]
=
0, the range is inclusive . Addresses from (DAC1)
to (DAC2)-1 fall within the range. Addresses from 0 to (DAC1)-1 and
(DAC2) to 0xFFFF_FFFF fall outside the range.
• When DBCR1[DA12X]
=
1, the range is exclusive . Addresses from 0 to
(DAC1)-1 and (DAC2) to 0xFFFF_FFFF fall within the range. Addresses
from (DAC1) to (DAC2)-1 fall outside the range.
Figure 9-8 shows the range specification based on the value of
DBCR1[DA12X]. No shading indicates addresses that are in range and gray-
shading indicates addresses that are out of range.
Table 9-9 summarizes the DBCR1 bits used to control DAC address-range
comparisons and the DBSR bits used to report their status.
The processor does not clear the DBSR status bits when DAC events fail to
occur. After a DAC event is recorded by a debugger, the corresponding status
bits should be cleared to prevent ambiguity when recording future debug
events.
DAC Events Caused by Cache Instructions
DAC events can be caused by the execution of cache-control instructions. The
following summarizes the type of DAC events that can occur when a cache-
control instruction is executed:
• Cache-control instructions that can modify data are treated as stores
0 (DAC1)-1 (DAC1) (DAC2)-1 (DAC2) 0xFFFF_FFFF
Inclusive Range, DBCR1[DA12X]
=
0
0 (DAC1)-1 (DAC1) (DAC2)-1 (DAC2) 0xFFFF_FFFF
Exclusive Range, DBCR1[DA12X]
=
1
Figure 9-8: DAC Address-Range Specification
Table 9-9:
DAC Address-Range Match Resources
Event Enable Bit
(DBCR1)
DBCR1
[DA12X]
Type of Access Checked
Event Status Bit
(DBSR)
D1R and/or D2R 0 Load (read) inclusive (DAC1) and (DAC2)-1 DR1 and/or DR2
D1W and/or D2W Store (write) inclusive (DAC1) and (DAC2)-1 DW1 and/or DW2
D1R and/or D2R 1 Load (read) exclusive (DAC1) and (DAC2)-1 DR1 and/or DR2
D1W and/or D2W Store (write) exclusive (DAC1) and (DAC2)-1 DW1 and/or DW2