Xilinx Virtex-II Pro PPC405, User Manual

Page: 466 / 562

774 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Appendix A: Register Summary
R
CCR0
Core-Configuration Register 0
947 0x3B3 0x27D 0b10011_11101 Yes Read/Write Undefined
ICDBDR Instruction-Cache Debug-Data Register 979 0x3D3 0x27E 0b10011_11110 Yes Read-Only Undefined
SPRG4 SPR General-Purpose Register 4 276 0x114 0x288 0b10100_01000 Yes Read/Write Undefined
IAC3 Instruction Address-Compare 3 948 0x3B4 0x29D 0b10100_11101 Yes Read/Write Undefined
ESR Exception-Syndrome Register 980 0x3D4 0x29E 0b10100_11110 Yes Read/Write 0x0000_0000
IAC1 Instruction Address-Compare 1 1012 0x3F4 0x29F 0b10100_11111 Yes Read/Write Undefined
SPRG5 SPR General-Purpose Register 5 277 0x115 0x2A8 0b10101_01000 Yes Read/Write Undefined
IAC2 Instruction Address-Compare 2 1013 0x3F5 0x2B5 0b10101_11111 Yes Read/Write Undefined
IAC4 Instruction Address-Compare 4 949 0x3B5 0x2BD 0b10101_11101 Yes Read/Write Undefined
DEAR Data-Error Address Register 981 0x3D5 0x2BE 0b10101_11110 Yes Read/Write Undefined
SPRG6 SPR General-Purpose Register 6 278 0x116 0x2C8 0b10110_01000 Yes Read/Write Undefined
DVC1 Data Value-Compare 1 950 0x3B6 0x2DD 0b10110_11101 Yes Read/Write Undefined
EVPR Exception-Vector Prefix Register 982 0x3D6 0x2DE 0b10110_11110 Yes Read/Write Undefined
DAC1 Data Address-Compare 1 1014 0x3F6 0x2DF 0b10110_11111 Yes Read/Write Undefined
SPRG7 SPR General-Purpose Register 7 279 0x117 0x2E8 0b10111_01000 Yes Read/Write Undefined
DVC2 Data Value-Compare 2 951 0x3B7 0x2FD 0b10111_11101 Yes Read/Write Undefined
DAC2 Data Address-Compare 2 1015 0x3F7 0x2FF 0b10111_11111 Yes Read/Write Undefined
TSR Timer-Status Register 984 0x3D8 0x31E 0b11000_11110 Yes Read/Clear Undefined
1
SGR Storage Guarded Register 953 0x3B9 0x33D 0b11001_11101 Yes Read/Write 0xFFFF_FFFF
SRR0 Save/Restore Register 0 26 0x01A 0x340 0b11010_00000 Yes Read/Write Undefined
DCWR Data-Cache Write-Through Register 954 0x3BA 0x35D 0b11010_11101 Yes Read/Write Undefined
TCR Timer-Control Register 986 0x3DA 0x35E 0b11010_11110 Yes Read/Write Undefined
2
DCCR Data-Cache Cacheability Register 1018 0x3FA 0x35F 0b11010_11111 Yes Read/Write 0x0000_0000
SRR1 Save/Restore Register 1 27 0x01B 0x360 0b11011_00000 Yes Read/Write Undefined
SLER Storage Little-Endian Register 955 0x3BB 0x37D 0b11011_11101 Yes Read/Write 0x0000_0000
PIT Programmable-Interval Timer 987 0x3DB 0x37E 0b11011_11110 Yes Read/Write Undefined
ICCR Instruction-Cache Cacheability
Register 1019 0x3FB 0x37F 0b11011_11111 Yes Read/Write 0x0000_0000
TBL Time-Base Lower 284 0x11C 0x388 0b11100_01000 Yes Write-Only Undefined
SU0R Storage User-Defined 0 Register 956 0x3BC 0x39D 0b11100_11101 Yes Read/Write 0x0000_0000
TBU Time-Base Upper 285 0x11D 0x3A8 0b11101_01000 Yes Write-Only Undefined
DBCR1 Debug-Control Register 1 957 0x3BD 0x3BD 0b11101_11101 Yes Read/Write 0x0000_0000
SRR2 Save/Restore Register 2 990 0x3DE 0x3DE 0b11110_11110 Yes Read/Write Undefined
PVR Processor-Version Register 287 0x11F 0x3E8 0b11111_01000 Yes Read-Only 0x2001_0820
SRR3 Save/Restore Register 3 991 0x3DF 0x3FE 0b11111_11110 Yes Read/Write Undefined
Table A-6: Special-Purpose Registers Sorted by SPRF (Continued)
Name Descriptive Name
SPRN SPRF
Privileged Access Reset Value
Dec Hex Hex Binary