Xilinx Virtex-II Pro PPC405, User Manual

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March 2002 Release www.xilinx.com 353
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Operand Conventions
R
Operand Alignment
The operand of a memory-access instruction has a natural alignment boundary equal to
the operand length. In other words, the
natural address of an operand is an integral
multiple of the operand length. A memory operand is said to be aligned if it is aligned on
its natural boundary, otherwise it is misaligned.
All instructions are words and are always aligned on word boundaries.
Table 2-1 shows the value required by the least-significant four address bits (bits 28:31) of
each data type for it to be aligned in memory. A value of x in a given bit position indicates
the address bit can have a value of 0 or 1.
The concept of alignment can be generally applied to any data in memory. For example, a
12-byte data item is said to be word aligned if its address is a multiple of four.
Some instructions require aligned memory operands. Also, alignment can affect
performance. For single-register memory access instructions, the best performance is
obtained when memory operands are aligned.
Alignment and Endian Storage Control
The endian storage-control attribute (E) does not affect how the processor handles operand
alignment. Data alignment is handled identically for accesses to big-endian and little-
endian memory regions. No special alignment exceptions occur when accessing data in
little-endian memory regions. However, alignment exceptions that apply to big-endian
memory accesses also apply to little-endian memory accesses.
Performance Effects of Operand Alignment
The performance of accesses varies depending on the following parameters:
• Operand size
• Operand alignment
• Boundary crossing:
-
None
- Cache block
- Page
To obtain the best performance across the widest range of PowerPC embedded-
environment implementations and PowerPC Book-E processor implementations,
programmers should assume the alignment performance effects described in
Figure 2-2 .
This table applies to both big-endian and little-endian accesses. Figure 2-2 also applies to
PowerPC processors running in the default big-endian mode. However, those same
processors suffer further performance degradation when running in PowerPC little-
endian mode.
Table 2-1: Memory Operand Alignment Requirements
Data Type Size
Aligned Address
Bits 28:31
Byte 8 Bits xxxx
Halfword 2 Bytes xxx 0
Word 4 Bytes xx 00
Doubleword 8 Bytes x 000