Xilinx Virtex-II Pro PPC405, User Manual

Page: 246 / 562

554 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
R
2. If the preceding DAC comparison detects a matching address, the data-
value accessed at that address must match the value contained in one of
the DVC
n registers, using the conditions specified by the DBCR1 register.
The DAC comparison performed in the first step is set up to perform exact-
address or address-range comparisons as described in the previous section
(
Data Address-Compare Debug Event ). However, the DAC comparison does
not cause a DAC debug event. Because DVC and DAC events share the same
DAC registers, control bits, and status bits, a DAC event is disabled when the
corresponding DVC event is enabled, as follows:
• If DVC1 events are enabled, DAC1 events are disabled.
• If DVC2 events are enabled, DAC2 events are disabled.
• If DVC1 and DVC2 events are enabled (as in range comparisons), DAC1
and DAC2 events are disabled.
Unlike DAC events, the DVC event occurs after the data-access instruction
executes. If debug interrupts are enabled, the SRR2 register is loaded with the
effective address of the instruction following the one that caused the DVC
event.
DVC events are enabled by loading a non-zero value (
≠
0b0000) into the byte-
enable controls of the corresponding DVC n register. A non-zero value loaded
into DBCR1[DV1BE] enables DVC1 events and a non-zero value loaded into
DBCR1[DV2BE] enables DVC2 events. Referring to
Figure 9-6, page 543 , the
byte-enables specify which DVC n register bytes participate in the DVC
comparison:
• DV n BE
0
controls participation of DVC n data-value byte 0.
• DV n BE
1
controls participation of DVC n data-value byte 1.
• DV n BE
2
controls participation of DVC n data-value byte 2.
• DV n BE
3
controls participation of DVC n data-value byte 3.
When a DV n BE bit is set to 1, the specified byte in DVC n is compared against
the corresponding operand byte. If the bit is cleared to 0, the specified byte is
not compared. If DV
n BE
=
0b0000, no bytes participate in the comparison and
the DVC n event is disabled.
The data-value compare-mode bits in DBCR1 control how the enabled DVC n
bytes are compared against the operand value. The DV1M bits control the
DVC1 comparison and the DV2M bits control the DVC2 comparison. The
modes defined by these two-bit fields are:
• 00—The effect of this mode is undefined and should not be used.
• 01—AND mode. All DVC n bytes selected by DV n BE must match the
corresponding operand bytes.
• 10—OR mode. At least one of the DVC n bytes selected by DV n BE must
match the corresponding operand byte.
• 11—AND–OR mode. This mode uses the following algorithm to
determine whether a DVC event occurs:
( DV n BE
0
∧
(DV n [byte_0] = data_value[byte_0])
∧
DV n BE
1
∧
(DV n [byte_1] = data_value[byte_1]))
∨
( DV n BE
2
∧
(DV n [byte_2] = data_value[byte_2])
∧
DV n BE
3
∧
(DV n [byte_3] = data_value[byte_3]))
This comparison mode is useful when the byte enables are set to 0b1111.
Here, a DVC event occurs if either the upper halfword or lower halfword
of the DVC
n register matches the corresponding operand halfword.
Table 9-11 shows example settings of DV1BE and DV1M and how they affect
detection of a DVC1 match.