590
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 11:
Instruction Set
R
bclr
Branch Conditional to Link Register
Description
The next instruction address (NIA) is the effective address of the branch target. The NIA is
formed by concatenating the 30 most-significant bits of the LR with two 0-bits on the right.
Program flow is transferred to the NIA. If the LK field contains 1, then the address of the
instruction following the branch instruction (CIA + 4) is loaded into the LR.
The BO field specifies whether the branch is conditional on the contents of the CTR and/or
the CR registers and how those conditions are tested. The BO field also specifies whether
the CTR is decremented. The encoding of the BO field is described in
. The BI field specifies which CR bit is tested if the branch is conditional
on the CR register.
Simplified mnemonics defined for this instruction are described in the following sections:
•
?<Fill in list after appendix is built>
Pseudocode
if BO
2
=
0 then
CTR
←
CTR
−
1
CTR_cond_met
←
BO
2
∨
((CTR
≠
0)
⊕
BO
3
))
CR_cond_met
←
BO
0
∨
(CR
B
I
=
BO
1
)
if CTR_cond_met
∧
CR_cond_met
then NIA
←
LR
0:29
||
0b00
else
NIA
←
CIA + 4
if LK
=
1 then
(LR)
←
CIA + 4
Registers Altered
•
CTR if BO
2
=
0.
•
LR if LK
=
1.
Exceptions
•
None.
Execution of any of the following invalid-instruction forms results in a boundedly-
undefined result rather than a program exception:
•
Reserved bits containing a non-zero value.
bclr
BO, BI
(LK=0)
bclrl
BO, BI
(LK=1)
XL Instruction Form
19
BO
BI
0
0
0
0
0
16
LK
0
6
1
1
1
6
2
1
3
1
