654
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 11:
Instruction Set
R
Registers Altered
•
r
D and subsequent GPRs as described above.
Exceptions
•
Data storage—if the access is prevented by no-access-allowed zone protection. This
only applies to accesses in user mode when data relocation is enabled.
•
Data TLB miss—if data relocation is enabled and a valid translation-entry
corresponding to the EA is not found in the TLB.
Execution of any of the following invalid-instruction forms results in a boundedly-
undefined result rather than a program exception:
•
r
A
is in the range of registers to be loaded, including the case
r
A
=
r
D
=
0. Bytes that
would have been loaded into
r
A are discarded.
•
Reserved bits containing a non-zero value.
Compatibility
This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is
implemented by all PowerPC processors.
