Xilinx Virtex-II Pro PPC405, User Manual

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384 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 3: User Programming Model
R
Store Instructions
Integer-store instructions read an operand from a GPR source register, r S, and write it into
memory. Store-with-update instructions are provided, but the following two rules apply:
• r A must not be equal to 0. If r A
=
0, the instruction form is invalid.
• If
r
S
=
r
A,
r
S is written to memory first, and then the effective address is loaded into
r
S.
In the PPC405, the above invalid instruction form produces a boundedly-undefined result.
In other PowerPC implementations, that form can cause a program exception.
Store Byte
Table 3-18 lists the PowerPC store byte instructions. These instructions store the lower-eight
bits of r S into the specified byte location in memory.
Store Halfword
Table 3-19 lists the PowerPC store halfword instructions. These instructions store the lower-
16 bits of r S into the specified halfword location in memory.
Table 3-18: Store Byte Instructions
Mnemonic Name Addressing Mode
Operand
Syntax
stb
Store Byte Register-indirect with immediate index
EA
=
( r A|0)
+
d
r
S,d(
r
A)
stbu Store Byte with Update Register-indirect with immediate index
EA
=
( r A)
+
d
r
A
←
EA
r A
≠
0
stbx Store Byte Indexed Register-indirect with index
EA
=
( r A|0)
+
( r B)
r S, r A, r B
stbux Store Byte with Update Indexed Register-indirect with index
EA
=
(
r
A)
+
(
r
B)
r
A
←
EA
r A
≠
0