March 2002 Release
331
Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
PPC405 Features
R
Privileged Mode
Privileged mode
allows programs to access all registers and execute all instructions
supported by the processor. Normally, the operating system and low-level device drivers
operate in this mode.
User Mode
User mode
restricts access to some registers and instructions. Normally, application
programs operate in this mode.
Address Translation Modes
The PPC405 also supports two modes of address translation: real and virtual. Refer to
, for more information on address translation.
Real Mode
In
real mode
, programs address physical memory directly.
Virtual Mode
In
virtual mode
, programs address virtual memory and virtual-memory addresses are
translated by the processor into physical-memory addresses. This allows programs to
access much larger address spaces than might be implemented in the system.
Addressing Modes
Whether the PPC405 is running in real mode or virtual mode, data addressing is supported
by the load and store instructions using one of the following addressing modes:
•
Register-indirect with immediate index—A base address is stored in a register, and a
displacement from the base address is specified as an immediate value in the
instruction.
•
Register-indirect with index—A base address is stored in a register, and a
displacement from the base address is stored in a second register.
•
Register indirect—The data address is stored in a register.
Instructions that use the two indexed forms of addressing also allow for automatic updates
to the base-address register. With these instruction forms, the new data address is
calculated, used in the load or store data access, and stored in the base-address register.
The data-addressing modes are described in
.
With sequential-instruction execution, the next-instruction address is calculated by adding
four bytes to the current-instruction address. In the case of branch instructions, however,
the next-instruction address is determined using one of four branch-addressing modes:
•
Branch to relative—The next-instruction address is at a location relative to the current-
instruction address.
•
Branch to absolute—The next-instruction address is at an absolute location in
memory.
•
Branch to link register—The next-instruction address is stored in the link register.
•
Branch to count register—The next-instruction address is stored in the count register.
The branch-addressing modes are described in
Branch-Target Address Calculation
Data Types
PPC405 instructions support byte, halfword, and word operands. Multiple-word operands
are supported by the load/store multiple instructions and byte strings are supported by
