March 2002 Release
715
Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
Alphabetical Instruction Listing
R
sc
System Call
Description
This instruction causes a system-call exception to occur. The contents of the MSR are
loaded into SRR1. The address of the instruction immediately following the
sc
instruction
is loaded into SRR0.
The MSR[WE, EE, PR, DR, IR] bits are cleared to 0.
The exception-vector address is used as the next-instruction address (NIA) and program
control is transferred to the NIA. The exception vector address is formed by concatenating
the high halfword of the exception-vector-prefix register (EVPR) to the left of 0x0C00. This
instruction is context synchronizing. Instructions fetched from the NIA use the new
context loaded into the MSR.
Pseudocode
(SRR1)
←
(MSR)
(MSR[WE, EE, PR, DR, IR])
←
0
(SRR0)
←
CIA + 4
Synchronize context
NIA
←
EVPR
0:15
|| 0x0C00
Registers Altered
•
SRR0.
•
SRR1.
•
MSR[WE, EE, PR, DR, IR].
Exceptions
•
System call—execution of this instruction.
Execution of any of the following invalid-instruction forms results in a boundedly-
undefined result rather than a program exception:
•
Reserved bits containing a non-zero value.
Compatibility
This instruction is defined by the PowerPC architecture, the PowerPC embedded-
environment architecture, and the PowerPC Book-E architecture. It is part of the user
instruction-set architecture (UISA) and the operating-environment architecture (OEA). It is
implemented by all PowerPC processors.
sc
SC Instruction Form
17
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
6
3
0
3
1
