Xilinx Virtex-II Pro PPC405, User Manual

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March 2002 Release www.xilinx.com 531
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Timer-Event Interrupts
R
- When set to 1, the TSR[WIS] bit can be updated and is used by the processor as
described below. When TSR[ENW]=1, the next watchdog time-out causes a
watchdog interrupt (if enabled) or forces a reset (if a reset is specified). The value
of the TSR[WIS] bit determines whether the action taken is an interrupt or a reset.
In this case, the watchdog time-out that causes an interrupt is often referred to as
the
second watchdog time-out .
The processor sets the TSR[ENW] bit but never clears it. Only software can clear the
bit.
• Watchdog-interrupt status , TSR[WIS]—This bit is used by the processor only when
TSR[ENW]=1. It indicates whether or not a watchdog interrupt occurred and controls
further watchdog interrupts and reset, as follows:
-
When cleared to 0, no watchdog interrupt occurred. The next watchdog time-out
can cause a watchdog interrupt to occur, if the interrupt is enabled. When
TSR[ENW]
=
1, the next time-out sets this bit to 1.
- When set to 1, a watchdog interrupt occurred or would have occurred if enabled.
The next watchdog time-out forces a reset if a reset condition is specified by
TCR[WRC].
The processor sets the TSR[WIS] bit but never clears it. Only software can clear the bit.
Figure 8-6 shows the watchdog-event state machine and the transitions described in the
previous paragraphs. The transitions for the interrupt handler and system service routines
(both shown as dashed lines) are described in the following paragraphs.
Watchdog time-outs can be used to recover from otherwise unrecoverable errors. In the
absence of software intervention, consecutive watchdog time-outs can cause a reset under
the control of TCR[WRC]. This happens when the watchdog-event state machine enters
the “Reset” state shown in
Figure 8-6 . After a reset, system software can determine the
cause of the unrecoverable error and take appropriate action.
If no errors occur, software must periodically update the state of the state machine to
prevent a reset.
Figure 8-6 , shows three possible methods for properly managing the state
machine:
• Method (1)—an interrupt handler manages the state machine.
Figure 8-6: Watchdog-Event State Machine
UG011_48_033101
Time-Out, No Interrupt
ENW=0
WIS=0
ENW=1
WIS=0
ENW=0
WIS=1
ENW=1
WIS=1
Time-Out, No Interrupt
Time-Out, Interrupt
(If Enabled)
Time-Out
Interrupt
Handler
(1)
Interrupt
Handler
(2)
System
Service
(3)
System
Service
(2)
Reset
TCR[WRC]