March 2002 Release
351
Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
Operand Conventions
R
Endian (E) Storage Attribute
The endian (E) storage attribute allows the PPC405 to support direct connection of little-
endian peripherals and memory containing little-endian instructions and data. An E
storage attribute is associated with every memory reference—instruction fetch, data load,
and data store. The E attribute specifies whether the memory region being accessed should
be interpreted as big endian (E = 0) or little endian (E = 1).
If virtual mode is enabled (MSR[IR] = 1 or MSR[DR] = 1), the E field in the corresponding
TLB entry defines the endianness of a memory region. When virtual mode is disabled
(MSR[IR] = 0 and MSR[DR] = 0), the SLER defines the endianness of a memory region. See
for more information on virtual memory, and
Storage Little-Endian Register (SLER)
for more information on the SLER.
When a memory region is defined as little endian, the processor accesses those bytes as if
they are arranged in true little-endian order. Unlike the little-endian mode defined by the
PowerPC architecture, no address modification is performed when accessing memory
regions designated as little endian. Instead, the PPC405 reorders the bytes as they are
transferred between the processor and memory.
On-the-fly reversal of bytes in little-endian memory regions is handled in one of two ways,
depending on whether the memory access is an instruction fetch or a data access (load or
store). The following sections describe byte reordering for both types of memory accesses.
Little-Endian Instruction Fetching
Instructions are word (four-byte) data types that are always aligned on word boundaries in
memory. Instructions stored in a big-endian memory region are arranged with the most-
significant byte (MSB) of the instruction word at the lowest byte address.
Consider the big-endian mapping of instruction
p
at address 0x00, where, for example,
p
is
an
add
r7,r7,r4 instruction (instruction opcode bytes are shown in hexadecimal on top,
with the corresponding byte address shown below):
In the little-endian mapping, instruction
p
is arranged with the least-significant byte (LSB)
of the instruction word at the lowest byte address:
The instruction decoder on the PPC405 assumes the instructions it receives are in big-
endian order. When an instruction is fetched from memory, the instruction must be placed
in the instruction queue in big-endian order so that the instruction is properly decoded.
When instructions are fetched from little-endian memory regions, the four bytes of an
instruction word are reversed by the processor before the instruction is decoded. This byte
reversal occurs between memory and the instruction-cache unit (ICU) and is transparent to
software. The ICU always stores instructions in big-endian order regardless of whether the
instruction-memory region is defined as big endian or little endian. This means the bytes
are already in the proper order when an instruction is transferred from the ICU to the
instruction decoder.
If the endian-storage attribute is changed, the affected memory region must be reloaded
with program and data structures using the new endian ordering. If the endian ordering of
MSB
LSB
7C
E7
22
14
0x00
0x01
0x02
0x03
LSB
MSB
14
22
E7
7C
0x00
0x01
0x02
0x03
