Xilinx Virtex-II Pro PPC405, User Manual

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March 2002 Release www.xilinx.com 613
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Alphabetical Instruction Listing
R
dcbt
Data Cache Block Touch
Description
An effective address (EA) is calculated by adding an index to a base address, which are
formed as follows:
• The contents of register r B are used as the index.
• If the r A field is 0, the base address is 0.
• If the r A field is not 0, the contents of register r A are used as the base address.
If EA is cachable but not in the data cache, the corresponding cacheline is loaded into the
data cache from main memory. If EA is already cached, or if the storage attributes indicate
EA is not cachable, no operation is performed.
This instruction is a hint to the processor that the program will likely load data from EA in
the near future. The processor can potentially improve performance by loading the
cacheline into the data cache.
Pseudocode
EA
←
( r A|0) + ( r B)
Prefetch data cacheline corresponding to EA
Registers Altered
• None.
Exceptions
This instruction is considered a “load” with respect to data-storage exceptions. However,
this instruction does not cause data storage exceptions or data TLB-miss exceptions. If
conditions occur that would otherwise cause these exceptions,
dcbt is treated as a no-
operation. This instruction is also considered a “load” with respect to data address-
compare (DAC) debug exceptions. Debug exceptions can occur as a result of executing this
instruction.
Execution of any of the following invalid-instruction forms results in a boundedly-
undefined result rather than a program exception:
• Reserved bits containing a non-zero value.
dcbt r A, r B
X Instruction Form
31 0 0 0 0 0 r A r B 278 0
0 6 1
1 1
6 2
1 3
1