370
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 3:
User Programming Model
R
Branch Conditional to Count Register
lists the PowerPC
branch-conditional to count-register
instructions. The BO field
specifies the condition tested by the branch, as shown in
. The BI field
specifies the CR bit used in the test. The branch-target address is read from the CTR, with
CTR[30:31] cleared to zero to form a word-aligned address. Using the 32-bit CTR as a
branch target gives these branches the ability to cover the full 4 GB address range.
Branch Prediction
Conditional branches alter program flow based on the value of bits in the CR. If a condition
is met by the CR bits, the branch instruction alters the next-instruction address non-
sequentially. Otherwise, the next-sequential instruction following the branch is executed.
When the processor encounters a conditional branch, it scans the execution pipelines to
determine whether an instruction in progress can affect the CR bit tested by the branch. If
no such instruction is found, the branch can be resolved immediately by checking the bit in
the CR and taking the action defined by the branch instruction.
However, if a CR-altering instruction is detected, the branch is considered unresolved until
the CR-altering instruction completes execution and writes its result to the CR. Prior to that
time, the processor can
predict
how the branch is resolved. First, the processor uses special
dynamic prediction
hardware to analyze instruction flow and branch history to predict
resolution of the current branch. If branches are predicted correctly, performance
improvements can be realized because instruction execution does not stall waiting for the
branch to be resolved. The PowerPC architecture provides software with the ability to
override (reverse) the dynamic prediction using a
static prediction
hint encoded in the
instruction opcode. This can be useful when it is known at compile time that a branch is
likely to behave contrary to what the processor expects. The use of static prediction is
described in the next section,
Specifying Branch-Prediction Behavior
When a prediction is made, instructions are fetched from the predicted execution path. If
the processor determines the prediction was incorrect after the CR-altering instruction
completes execution, all instructions fetched as a result of the prediction are discarded by
the processor. Instruction fetch is restarted along the correct path. If the prediction was
correct, instruction fetch and execution proceed normally along the predicted (and now
resolved) path.
Branch prediction is most effective when the branch-target address is computed well in
advance of resolving the branch. If a branch instruction contains immediate addressing
operands, the processor can compute the branch-target address ahead of branch
resolution. If the branch instruction uses the LR or CTR for addressing, it is important that
the register is loaded by software sufficiently ahead of the branch instruction.
Specifying Branch-Prediction Behavior
All PowerPC processors predict a conditional branch as taken using the following rules:
•
For the
bc
x
instruction with a negative value in the displacement operand, the branch
is predicted taken.
•
For all other branch-conditional instructions (
bc
x
with a non-negative value in the
displacement operand,
bclr
x
, or
bcctr
x
), the branch is predicted not taken.
Table 3-9:
Branch-Conditional to Count-Register Instructions
Mnemonic
Name
Operation
Operand
Syntax
bcctr
Branch Conditional to Count Register
Branch-conditional to address in CTR.
BO,BI
bcctrl
Branch Conditional to Count Register
and Link
Branch-conditional to address in CTR. LR is
updated with the address of the instruction
following the branch.
