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Appendix E:

PowerPC

6xx/7xx Compatibility

DCCR

Data-cache cacheability register

Storage control

DCWR

Data-cache write-through register

ICCR

Instruction-cache cacheability register

SGR

Storage Guarded Register

SLER

Storage Little-Endian Register

SU0R

Storage User-Defined 0 Register

ZPR

Zone-Protection Register

DCRs

Device control registers

External device control

DEAR

Data-error address register

Exception and interrupt processing

ESR

Exception-syndrome register

EVPR

Exception-vector prefix register

SRR2

Save/restore register 2

SRR3

Save/restore register 3

PIT

Programmable-Interval Timer

Timer resources

TCR

Timer-Control Register

TSR

Timer-Status Register

DAC

Data address-compare registers

Debugging

DBCR

Debug-control registers

DBSR

Debug-status register

DVC

Data value-compare registers

IAC

Instruction address-compare registers

ICDBDR

Instruction-cache debug-data register

Table E-2:

6xx/7xx Registers Not Supported by 40x Processors

Name

Description

Purpose

HID

Hardware implementation registers

Processor configuration

DBAT

Data BATs

Memory management

IBAT

Instruction BATs

SDR1

Page table base address

Segment registers

EAR

External address register

External device control

DAR

Data address register

Exception and interrupt processing

DSISR

Data storage interrupt status register

DEC

Decrementer

Timer resources

DABR

Data-address breakpoint register

Exception and interrupt processing

IABR

Instruction-address breakpoint register

Table E-1:

40x Registers Not Supported by 6xx/7xx Processors

Name

Description

Purpose

Summary of Contents for Virtex-II Pro PPC405

Page 1: ...R Volume 2 a PPC405 User Manual Virtex II Pro Platform FPGA Developer s Kit March 2002 Release...

Page 2: ...CodePack All other trademarks are the property of their respective owners Xilinx does not assume any liability arising out of the application or use of any product described or shown herein nor does...

Page 3: ...entation of the PowerPC embedded environment architecture This chapter also contains an overview of the features supported by the PPC405 Chapter 2 Operational Concepts introduces the processor operati...

Page 4: ...PC 6xx 7xx Compatibility describes the programming model differences between the PPC405 and PowerPC 6xx and 7xx series processors Appendix F PowerPC Book E Compatibility describes the programming mode...

Page 5: ...tions Continued Convention Definition Table P 2 Instruction Field Definitions Field Location Description AA 30 Absolute address bit branch instructions 0 The immediate field represents an address rela...

Page 6: ...e address of the next instruction MB 21 25 Mask begin Used in rotate and mask instructions to specify the beginning bit of a mask ME 26 30 Mask end Used in rotate and mask instructions to specify the...

Page 7: ...ield Extended opcodes in decimal appear in the instruction format diagrams presented with individual instructions The XO field name does not appear in instruction descriptions XO 22 30 Extended opcode...

Page 8: ...he result of extending n on the left with sign bits if then else Conditional execution if condition then a else b where a and b represent one or more pseudocode statements Indenting indicates the rang...

Page 9: ...se register number formed using the split TBRF field in a mftb instruction Table P 3 Pseudocode Conventions Continued Convention Definition Table P 4 Operator Precedence Operators Associativity REGIST...

Page 10: ...register rn Specifies GPR n r15 for example SGR Storage guarded register SLER Storage little endian register SPRGn SPR general purpose register n SRRn Save restore register n SU0R Storage user defined...

Page 11: ...ructions between the processor and PLB It is used when cache misses occur and when access to non cacheable memory occurs flush A cache or TLB operation that involves writing back a modified entry to m...

Page 12: ...program or portion of a program and any data required for the program to run problem state Synonym for user mode real address Synonym for physical address scalar Individual data objects and instructi...

Page 13: ...6 Published by Warthman Associates Palo Alto CA ISBN 0 9649654 0 2 Optimizing PowerPC Code Programming the PowerPC Chip in Assembly Language by Gary Kacmarcik ASIN 0201408392 PowerPC Programming Pocke...

Page 14: ...322 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation Preface R...

Page 15: ...Overview The PowerPC architecture is a 64 bit architecture with a 32 bit subset The material in this document only covers aspects of the 32 bit architecture implemented by the PPC405 In general the P...

Page 16: ...chitecture are defined in Table 1 1 The PowerPC architecture requires that all PowerPC implementations adhere to the UISA offering compatibility among all PowerPC application programs However differen...

Page 17: ...t one level of the architecture and defined more specifically at another For example the UISA defines conditions that can cause an alignment exception and the OEA specifies the exception itself Featur...

Page 18: ...s do not include the special 64 bit extensions to the PowerPC UISA Also floating point support can be provided either in hardware or software by PowerPC embedded environment processors Figure 1 1 show...

Page 19: ...programs to create or modify code to manage storage coherency and to optimize memory access performance It defines the cache and memory models the timekeeping resources from a user perspective and res...

Page 20: ...uctions Exception model Dual level interrupt structure supporting various exception types Specification of interrupt priorities and masking Privileged SPRs for controlling and handling exceptions Inte...

Page 21: ...ed software is in general not compatible but the differences are relatively minor Software developers who are concerned with cross compatibility of privileged software between the PPC405 and PowerPC B...

Page 22: ...uring cacheline fills and flushes Support for on chip memory OCM that can provide memory access performance identical to a cache hit Flexible memory management Translation of the 4 GB logical address...

Page 23: ...mmediate value in the instruction Register indirect with index A base address is stored in a register and a displacement from the base address is stored in a second register Register indirect The data...

Page 24: ...d by that operand For example if the four bytes in a word operand occupy addresses 4 5 6 and 7 the word address is 4 The PPC405 supports both big endian an operand s most significant byte is at the lo...

Page 25: ...igure 1 2 PPC405 Registers UG011_51_033101 MSR Machine State Register CCR0 Core Configuration Register SPR General Purpose Registers SPRG0 SPRG1 SPRG2 SPRG3 SPRG4 SPRG5 SPRG6 SPRG7 Memory Management R...

Page 26: ...ructions can set CR0 and compare instructions can set any CR field Additional instructions are provided to perform logical operations and tests on CR fields and bits within the fields The CR can be ac...

Page 27: ...register or count register The default prediction can be overridden by software at assembly or compile time This capability is described further in Branch Prediction page 370 The PPC405 has a single...

Page 28: ...he PPC405 Memory Management Unit The PPC405 supports 4 GB of flat non segmented address space The memory management unit MMU provides address translation protection functions and storage attribute con...

Page 29: ...cacheline fill minimizing execution stalls caused by instruction cache misses When the ICU is accessed four instructions are read from the appropriate cacheline and placed temporarily in a line buffer...

Page 30: ...r appears to be stopped Real time trace mode which supports event triggering for real time tracing Debug events are supported that allow developers to manage the debug process Debug modes and debug ev...

Page 31: ...al processor state to facilitate software debugging This capability complies with the IEEE 1149 1 specification for vendor specific extensions and is therefore compatible with standard JTAG hardware f...

Page 32: ...340 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation Chapter 1 Introduction to the PPC405 R...

Page 33: ...sor systems The weakly consistent memory model allows system bus operations to be reordered dynamically The goal of reordering bus operations is to reduce the effect of memory latency and improving ov...

Page 34: ...e the operation complete execution in the context they were initiated This includes privilege level translation mode and memory protection All instructions following the operation complete execution i...

Page 35: ...leged mode User mode The processor operating mode is controlled by the privilege level field in the machine state register MSR PR When MSR PR 0 the processor operates in privileged mode When MSR PR 1...

Page 36: ...ion address NIA when it is used to fetch an instruction sequentially or as the result of a branch The input values and method used by the processor to calculate an EA depend on the instruction that is...

Page 37: ...d to translate the addresses generated by programs into physical memory addresses Memory management also consists of the mechanisms used to characterize memory region behavior also referred to as stor...

Page 38: ...essing Modes Programs can use 32 bit effective addresses to reference the 4 GB physical address space using one of two addressing modes Real mode Virtual mode Real mode and virtual mode are enabled an...

Page 39: ...bit is numbered 31 A bit set to 1 has a numerical value associated with its position b relative to the least significant bit lsb This value is equal to 2 lsb b For example if bit 5 is set to 1 in a b...

Page 40: ...3 0 31 0x03 0x02 0x01 0x00 0x04 LSB MSB Byte 0 Byte 1 Byte 2 Byte 3 Memory Content Memory Address Halfword Byte 0 Byte 1 0 31 0x03 0x02 0x01 0x00 0x04 LSB MSB Byte 0 Byte 1 Byte Byte 0 0 31 0x00 0x03...

Page 41: ...equential byte address is assigned to the next lowest byte and so on The term little endian is used because the little end of the scalar when considered as a binary number comes first in memory The fo...

Page 42: ...nment architecture and PowerPC Book E architecture Little endian mode defined by the PowerPC architecture is not implemented by the PPC405 Little endian mode does not support true little endian memory...

Page 43: ...reordering for both types of memory accesses Little Endian Instruction Fetching Instructions are word four byte data types that are always aligned on word boundaries in memory Instructions stored in a...

Page 44: ...ata item is a byte is not reversed when the big endian and little endian mappings are compared For example the character A is located at address 14 in both the big endian and little endian mappings In...

Page 45: ...e aligned Alignment and Endian Storage Control The endian storage control attribute E does not affect how the processor handles operand alignment Data alignment is handled identically for accesses to...

Page 46: ...lignment Interrupt 0x0600 page 510 for more information Instruction Conventions Instruction Forms Opcode tables and instruction listings often contain information regarding the instruction form This i...

Page 47: ...lass Defined instructions contain all the instructions defined by the PowerPC architecture Defined instructions are guaranteed to be supported by all implementations of the PowerPC architecture The on...

Page 48: ...served instruction as described in the following section An attempt to execute an illegal instruction causes an illegal instruction error program exception With the exception of an instruction consist...

Page 49: ...ntations The last three columns indicate which PPC405 instructions are part of the allocated instruction class Support of these instructions by PowerPC Book E processors is implementation dependent De...

Page 50: ...Class The reserved instruction class consists of all instruction primary opcodes and associated extended opcodes if applicable that do not belong to either the defined class or the allocated class Pre...

Page 51: ...are typically creates a context execution environment that protects itself and other applications from the effects of an errant application program The remaining chapters in this book generally descri...

Page 52: ...A Special Purpose Registers page 770 for a complete list of all SPRs user and privileged supported by the PPC405 Simplified instruction mnemonics are available for the mtspr and mfspr instructions fo...

Page 53: ...pecific bits in the CR The integer arithmetic instructions can update CR0 to reflect their result The integer compare instructions can update a specific CR field to reflect their result Conditional br...

Page 54: ...bit is set when the result is positive and not zero otherwise it is cleared 2 EQ Zero 0 Result is not equal to zero 1 Result is equal to zero This bit is set when the result is zero otherwise it is cl...

Page 55: ...Table 3 3 Fixed Point Exception Register XER Bit Definitions Bit Name Function Description 0 SO Summary overflow 0 No overflow occurred 1 Overflow occurred SO is set to 1 whenever an instruction excep...

Page 56: ...unt that is decremented by a conditional branch instruction with an appropriately coded BO opcode field The value in the CTR wraps to 0xFFFF_FFFF if the value in the register is 0 prior to the decreme...

Page 57: ...G7 263 0x107 These registers can be read using the mfspr instruction In privileged mode system software accesses these registers using different SPR numbers see page 432 Time Base Registers The time b...

Page 58: ...on storage interrupt handler to be invoked Alignment Exception An attempt to access memory with an invalid effective address alignment for the specific instruction causes the alignment interrupt handl...

Page 59: ...R or fields within the branch instruction Optionally a branch return address can be automatically loaded into the LR by setting the LK instruction opcode bit to 1 This option is useful for specifying...

Page 60: ...n Branch Unconditional Table 3 6 lists the PowerPC unconditional branch instructions These branches specify a 26 bit signed displacement to the branch target address by appending the 24 bit LI instruc...

Page 61: ...anch Unconditional Instructions Mnemonic Name Operation Operand Syntax b Branch Branch to relative address tgt_addr ba Branch Absolute Branch to absolute address bl Branch and Link Branch to relative...

Page 62: ...rchitecture provides software with the ability to override reverse the dynamic prediction using a static prediction hint encoded in the instruction opcode This can be useful when it is known at compil...

Page 63: ...ed by the processor Setting the y bit to 1 reverses the above behavior For branch always encoding BO 0 BO 2 branch prediction cannot be reversed no y bit is recognized The sign of the displacement ope...

Page 64: ...mpute the effective address EA of the next instruction using the following addressing modes Branch to relative conditional and unconditional Branch to absolute conditional and unconditional Branch to...

Page 65: ...30 to 0 The link register update option is enabled by setting the LK instruction field bit 31 to 1 This option causes the effective address of the instruction following the branch instruction to be lo...

Page 66: ...ons that use branch conditional to absolute addressing generate the next instruction address by appending 0b00 to the immediate displacement operand BD and sign extending the result Branches using thi...

Page 67: ...anch conditional to count register instruction generates the next instruction address by reading the contents of the CTR and clearing the two low order bits to zero The link register update option is...

Page 68: ...vice routine Executing the sc instruction causes a system call exception to occur See System Call Interrupt 0x0C00 page 514 for more information on the operation of this instruction Table 3 10 Conditi...

Page 69: ...tions See Trap Instructions page 832 for more information The TO operand field in the system trap instructions specifies the test conditions performed on the remaining two operands Multiple test condi...

Page 70: ...of three addressing modes register indirect with immediate index register indirect with index or register indirect These addressing modes are described in the following sections For some instructions...

Page 71: ...of these two registers are added to generate the effective address If the rA instruction field is 0 specifying r0 a value of zero rather than the contents of r0 is added to rB The option to specify rA...

Page 72: ...o to be generated The option to specify rA or 0 is shown in the instruction descriptions as rA 0 Figure 3 19 shows how an effective address is generated when using register indirect addressing Figure...

Page 73: ...PC405 the above invalid instruction forms produce a boundedly undefined result In other PowerPC implementations those forms can cause a program exception Load Byte and Zero Table 3 14 lists the PowerP...

Page 74: ...oad Halfword and Zero Register indirect with immediate index EA rA 0 d rD d rA lhzu Load Halfword and Zero with Update Register indirect with immediate index EA rA d rA EA rA 0 rA rD lhzx Load Halfwor...

Page 75: ...ng Mode Operand Syntax lha Load Halfword Algebraic Register indirect with immediate index EA rA 0 d rD d rA lhau Load Halfword Algebraic with Update Register indirect with immediate index EA rA d rA E...

Page 76: ...C implementations that form can cause a program exception Store Byte Table 3 18 lists the PowerPC store byte instructions These instructions store the lower eight bits of rS into the specified byte lo...

Page 77: ...a in little endian order Likewise when used in a system operating with little endian byte order these instructions have the effect of loading Table 3 19 Store Halfword Instructions Mnemonic Name Addre...

Page 78: ...n Table 3 21 Load and Store with Byte Reverse Instructions Mnemonic Name Addressing Mode Operand Syntax lhbrx Load Halfword Byte Reverse Indexed Register indirect with index EA rA 0 rB rD rA rB lwbrx...

Page 79: ...PowerPC load and store string instructions and their addressing modes See the individual instruction listings in Chapter 11 Instruction Set for more information on their operation and restrictions on...

Page 80: ...NB 0 then n 32 The indexed forms take the byte count from XER 25 31 Unlike the immediate forms if XER 25 31 0 then n 0 For the lswx instruction the contents of rD are undefined if n 0 The n bytes are...

Page 81: ...signed integers The following types of integer instructions are supported by the PowerPC architecture Arithmetic Instructions Logical Instructions Compare Instructions Rotate Instructions Shift Instru...

Page 82: ...and in some cases between GPRs and signed immediate values Integer Addition Instructions Table 3 24 shows the PowerPC integer addition instructions The instructions in this table are grouped by the t...

Page 83: ...A 0 SIMM 0x0000 addis Add Immediate Shifted XER and CR0 are not updated rD rA SIMM Add Extended Instructions rD is loaded with the sum rA rB XER CA adde Add Extended XER CA is updated to reflect the r...

Page 84: ...is represented by the register pair r3 r4 where r3 contains the most significant 32 bits of i and r4 contains the least significant 32 bits The 64 bit integer j is similarly represented by the registe...

Page 85: ...rB subfe Subtract from Extended and Record XER CA and CR0 are updated to reflect the re sult subfeo Subtract from Extended with Overflow Enabled XER CA OV SO are updated to reflect the result subfeo...

Page 86: ...bled and Record XER OV SO and CR0 are updated to reflect the result Table 3 27 Multiply Instructions Mnemonic Name Operation Operand Syntax Multiply Low Word Instructions rD is loaded with the low 32...

Page 87: ...tination register rather than a source register rS is used to specify one of the source registers AND and NAND Instructions Table 3 29 shows the PowerPC AND and NAND instructions For each type of inst...

Page 88: ...i AND Immediate and Record CR0 is updated to reflect the result rA rS UIMM AND Immediate Shifted Instructions rA is loaded with the logical result rS AND UIMM 0x0000 andis AND Immediate Shifted and Re...

Page 89: ...OR UIMM 0x0000 oris OR Immediate Shifted CR0 is not updated rA rS UIMM OR with Complement Instructions rA is loaded with the logical result rS OR rB orc OR with Complement CR0 is not updated rA rS rB...

Page 90: ...ion on the CR fields The second operand specifies the operand length This is referred to the L bit in the compare instruction encoding When using the compare instructions on 32 bit PowerPC implementat...

Page 91: ...ion has the record Rc bit set to 1 in the instruction encoding CR0 CR 0 3 is updated to reflect the result of the operation A set Rc bit is indicated by the suffix in the instruction mnemonic Rotate i...

Page 92: ...r is summarized as if MB ME then mask MB ME 1 s mask all remaining bits 0 s else mask MB 31 ones mask 0 ME ones mask all remaining bits 0 s Figure 3 23 shows the generated mask for both cases Rotate L...

Page 93: ...left rotated 16 bits and the result is written to rA after ANDing with the mask This has the effect of extracting byte 0 from rS rS 0 7 and placing it in byte 2 of rA rA 16 23 Rotate Left then Mask In...

Page 94: ...ll other bit positions The example shows the original contents of the destination register rA and the source register rS rS is rotated 16 bits and the result is inserted into rA after ANDing with the...

Page 95: ...instructions In the operand syntax for shift instructions the rA operand specifies the destination register rather than a source register rS is used to specify the source register Simplified mnemonics...

Page 96: ...tion Figure 3 26 Logical Shift Examples UG011_18_033101 Shift by 7 bits rS 0 31 1000_0111_0110_0101_0100_0011_0010_0001 rA 0 31 0000_0001_0000_1110_1100_1010_1000_0110 0 31 0000_0001_0000_1110_1100_10...

Page 97: ...instructions negative multiply accumulate instructions and multiply halfword instructions Modulo and Saturating Arithmetic The multiply accumulate and negative multiply accumulate instructions produc...

Page 98: ...it intermediate result Generally rD is loaded with the lower 32 bits of the 33 bit intermediate result However if the instruction performs saturating arithmetic and the intermediate result overflows r...

Page 99: ...bits of this result are stored in rD Otherwise the nearest representable value is stored in rD macchwsu Multiply Accumulate Cross Halfword to Word Saturate Unsigned XER and CR0 are not updated rD rA...

Page 100: ...dicates the multiply accumulate operation performed The column also shows on an instruction by instruction basis how the XER and CR registers are updated if at all Figure 3 28 Multiply Accumulate Cros...

Page 101: ...ts of this result are stored in rD Otherwise the nearest representable value is stored in rD machhwsu Multiply Accumulate High Halfword to Word Saturate Unsigned XER and CR0 are not updated rD rA rB m...

Page 102: ...egister rD producing a 33 bit intermediate result Generally rD is loaded with the lower 32 bits of the 33 bit intermediate result However if the instruction performs saturating arithmetic and the inte...

Page 103: ...Otherwise the nearest representable value is stored in rD maclhws Multiply Accumulate Low Halfword to Word Saturate Signed XER and CR0 are not updated rD rA rB maclhws Multiply Accumulate Low Halfword...

Page 104: ...o Word Modulo Unsigned XER and CR0 are not updated rD rA rB maclhwu Multiply Accumulate Low Halfword to Word Modulo Unsigned and Record CR0 is updated to reflect the result maclhwuo Multiply Accumulat...

Page 105: ...This product is negated and added to the value in the destination register rD producing a 33 bit intermediate result this is the same as subtracting the product from rD Generally rD is loaded with th...

Page 106: ...the result nmacchwo Negative Multiply Accumulate Cross Halfword to Word Modulo Signed with Overflow Enabled and Record XER OV SO and CR0 are updated to reflect the result Negative Multiply Accumulate...

Page 107: ...tination register rD producing a 33 bit intermediate result this is the same as subtracting the product from rD Generally rD is loaded with the lower 32 bits of the 33 bit intermediate result However...

Page 108: ...h Overflow Enabled XER OV SO are updated to reflect the result nmachhwo Negative Multiply Accumulate High Halfword to Word Modulo Signed with Overflow Enabled and Record XER OV SO and CR0 are updated...

Page 109: ...result this is the same as subtracting the product from rD Generally rD is loaded with the lower 32 bits of the 33 bit intermediate result However if the instruction performs saturating arithmetic an...

Page 110: ...the result nmaclhwo Negative Multiply Accumulate Low Halfword to Word Modulo Signed with Overflow Enabled and Record XER OV SO and CR0 are updated to reflect the result Negative Multiply Accumulate L...

Page 111: ...depending on the instruction For each type of instruction shown in Table 3 46 the Operation column indicates the multiply operation performed The column also shows on an instruction by instruction bas...

Page 112: ...f at all The XER register is not updated by these instructions Multiply Cross Halfword to Word Unsigned Instructions rD is loaded with the unsigned product rA 16 31 rB 0 15 mulchwu Multiply Cross Half...

Page 113: ...updated if at all The XER register is not updated by these instructions Multiply High Halfword to Word Unsigned Instructions rD is loaded with the unsigned product rA 0 15 rB 0 15 mulhhwu Multiply Hi...

Page 114: ...egal instruction and call the appropriate library routines to emulate the floating point instruction using integer instructions This method is not preferred due to the overhead associated with executi...

Page 115: ...4 bit CR fields with the most significant CRM bit corresponding to CR0 and the least significant CRM bit corresponding to CR7 When mtcrf is executed a CR field is loaded with the corresponding bits i...

Page 116: ...tion For more information see Split Field Notation page 571 Synchronizing Instructions Table 3 51 lists the PowerPC synchronization instructions The types of synchronization defined by the PowerPC arc...

Page 117: ...only when necessary Synchronization Effects of PowerPC Instructions Additional PowerPC instructions can cause synchronizing operations to occur All instructions that result in some form of synchroniza...

Page 118: ...If the reservation exists when the store is executed the store is performed and CR0 EQ is set to 1 If the reservation does not exist when the store is executed the target memory location is not modifi...

Page 119: ...supported on all PowerPC implementations It is good programming practice to always specify identical addresses for lwarx and stwcx pairs The PPC405 can maintain only one reservation at a time The add...

Page 120: ...428 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation Chapter 3 User Programming Model R...

Page 121: ...r 8 Timer Resources describes the time base and timer registers Chapter 9 Debugging describes the resources available in the PPC405 for debugging software and hardware Privileged Registers Figure 4 1...

Page 122: ...1 SPR 0x111 SPRG2 SPR 0x112 SPRG3 SPR 0x113 SPRG4 SPR 0x114 SPRG5 SPR 0x115 SPRG6 SPR 0x116 SPRG7 SPR 0x117 PVR Processor Version Register SPR 0x11F Memory Management Registers PID SPR 0x3B1 ZPR SPR 0...

Page 123: ...ation on these instructions The MSR is also modified during execution of the system call instruction sc return from interrupt instructions rfi and rfci and by the exception mechanism during a control...

Page 124: ...0200 page 504 for more information 20 FE0 Floating Point Exception Mode 0 Unsupported This bit is unsupported and ignored by the PPC405 Software should clear this bit to 0 21 DWE Debug Wait Enable 0 D...

Page 125: ...ectively The bit definitions are shown in Table 4 2 The PVR is a privileged read only SPR with an address of 287 0x11F It is read using the mfspr instruction Write access is not supported 0 31 General...

Page 126: ...system call interrupt handler determines which system service routine to call and whether the calling application has permission to call that service If permission is granted the system call interrupt...

Page 127: ...tion page 342 for more information Special Purpose Register Instructions The special purpose register instructions shown in Table 4 6 are used to read and write the special purpose registers SPRs usin...

Page 128: ...se of the processor wait state Wait state is a low power operating mode that can be used to conserve processor energy when the processor is not busy Wait state is entered when software sets the wait s...

Page 129: ...sually through a memory controller The PowerPC architecture does not define the type organization implementation or existence of internal or external caches The cache structure of other PowerPC proces...

Page 130: ...pipelining and prefetching for cache misses and non cacheable requests Buffering of up to eight non cacheable instructions in the fill buffer Support for non cacheable hits into the fill buffer Flash...

Page 131: ...t have a dirty bit The 512 total lines of 32 bytes each yields a 16 KB cache size Data is selected from the data cache using fields within the data address Likewise an instruction is selected from the...

Page 132: ...two tags are present in a congruence class The tag field in the data address is compared to both tags in the congruence class A hit occurs when the data address tag field is equal to one of the two ta...

Page 133: ...the ICU examines the instruction cache for a hit When a hit occurs the cacheline is read from the instruction cache and loaded into the line buffer Individual instructions are sent from the line buffe...

Page 134: ...onfiguration Register page 459 describes additional software controls that can be used to manage instruction prefetching from cacheable and non cacheable memory Instruction Cache Hint Instruction The...

Page 135: ...resulting in as many as eight synonyms 4 KB pages one bit EA19 is used in indexing and tag comparison resulting in two possible synonyms The following two options are available for preventing cache sy...

Page 136: ...a cacheline flush to occur prior to loading the cacheline from the fill buffer A cacheline flush updates system memory with the modified data from the cache All 32 bytes in a cacheline are written seq...

Page 137: ...contiguous addresses Loads from non cacheable memory and those that do not allocate cachelines as described above can be programmed to generate eight word PLB requests or to generate only the number...

Page 138: ...if the first load cannot be completed immediately If a subsequent DCU request of any kind is made it is not accepted until the previous loads are completed by the DCU A store to non cacheable memory...

Page 139: ...ine corresponding to the specified address Data cache block zero dcbz This instruction allocates a cacheline corresponding to the specified address and clears the cacheline contents to zero It can be...

Page 140: ...No other access is guaranteed to be atomic particularly the following Load and store operations using unaligned operands Accesses resulting from execution of the lmw stmw lswi lswx stswi or stswx ins...

Page 141: ...ve accesses are inappropriate For example an attempt to fetch instructions from addresses that do not contain instructions can cause a program to fail Speculatively reading data from a memory mapped I...

Page 142: ...ents speculative accesses from occurring outside the appropriate regions The system call and interrupt return instructions sc rfi and rfci are not recognized by the processor as breaks in program flow...

Page 143: ...controls the caching policy of a memory region When the W attribute is cleared to 0 the memory region has a write back caching policy Writes that hit the cache update the cacheline but they do not upd...

Page 144: ...ion condition can be enabled using the U0 exception enable bit U0XE in the CCR0 register see Core Configuration Register page 459 When CCR0 U0XE 1 a store to memory locations with U0 1 cause a data st...

Page 145: ...bits in the DCWR are cleared to 0 This establishes a write back caching policy for all real mode memory The DCWR is a privileged SPR with an address of 954 0x3BA and can be read and written using the...

Page 146: ...d and written using the mfspr and mtspr instructions Instruction Cache Cacheability Register ICCR The instruction cache cacheability register ICCR specifies real mode instruction memory cacheability t...

Page 147: ...2 containing compressed instructions In those implementations memory regions with U0 1 contain compressed instructions and memory regions with U0 0 contain uncompressed instructions System software c...

Page 148: ...on name the term cache block often appears A cache block is synonymous with a cacheline Table 5 3 summarizes which cache control instructions are privileged and which instructions can be executed in u...

Page 149: ...g EA rA 0 rB rA rB icbt Instruction Cache Block Touch If the instruction specified by the effective address EA is cacheable and is not currently cached by the instruction cache the cacheline containin...

Page 150: ...EA is cached by the data cache the cacheline containing that byte is invalidated If the cacheline is modified dirty those modifications are lost EA is calculated using register indirect with index add...

Page 151: ...on Cache debug features Figure 5 13 shows the format of the CCR0 The fields in CCR0 are defined as shown in Table 5 6 dcbz Data Cache Block Clear to Zero An effective address EA is calculated using re...

Page 152: ...e data cache unit onto the processor local bus PLB Bit 0 is controlled by the processor and cannot be controlled by software See PLB Request Priority page 461 for more information 10 11 IPP ICU PLB Pr...

Page 153: ...available GPRs 22 NCRS Non Cacheable Request Size 0 Request size is four words 1 Request size is eight words Specifies the number of instructions requested from non cacheable memory when an instructio...

Page 154: ...ht instructions are touched into a single cacheline This function example contains seven instructions If more than eight instructions are required additional lines must be touched into the cache icbt...

Page 155: ...present in the cache are not updated For example when a DMA controller reads and writes cacheable system memory coherency can be lost because The processor does not automatically supply the DMA contr...

Page 156: ...ndicates a replacement value in the cache unrelated to the program Next assume an external device updates the words at system memory addresses 0x100C 0x1024 while at the same time a cacheline reload f...

Page 157: ...mory regions It is recommended that the alignment and size of shared memory regions be a multiple of the cacheline size By configuring all shared memory regions to start on a cacheline boundary and sp...

Page 158: ...smaller than the data cache The following code sequence is an example of how shared memory can be flushed from the data cache r1 start of shared memory region r2 end of shared memory region loop dcbf...

Page 159: ...tes executable code from one cacheable memory location to another requires the same coherency treatment as self modifying code Although instructions are not changed they are treated as data by the pro...

Page 160: ...its EA22 26 A way is selected from the congruence class using the cache way select field CWS in the CCR0 register CCR0 CWS 0 selects way A and CCR0 CWS 1 selects way B The cacheline information in the...

Page 161: ...ngruence class and way is loaded into the destination GPR rD Figure 5 15 shows the format of the cache information loaded into rD The information fields loaded in rD are defined as shown in Table 5 8...

Page 162: ...470 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation Chapter 5 Memory System Management R...

Page 163: ...rovides greater control over memory protection Blocks of memory as small as 1 KB can be individually protected from unauthorized access Protection and relocation enable system software to support mult...

Page 164: ...ess protection is limited the U0 storage attribute can be used for write protection Implementation of a real mode memory manager is more straightforward than a virtual mode memory manager Real mode is...

Page 165: ...LB When translating a virtual address the MMU examines the page translation entries for a matching VPN PID and EPN Rather than examining all entries in the table only entries contained in the processo...

Page 166: ...ticular embedded system Both the page table size and access time can be optimized Independent page sizes can be used for application modules device drivers system service routines and data Independent...

Page 167: ...lation into a physical page determine the protection characteristics of the page and specify the storage attributes associated with the page The PPC405 TLB is physically implemented as three separate...

Page 168: ...TLBHI also referred to as the tag entry and TLBLO also referred to as the data entry The fields within a TLB entry are categorized as follows Virtual page identification These fields identify the pag...

Page 169: ...sed by all processes Physical Page Identification Fields The physical page identification portion of a TLB entry contains the following field RPN Physical page number or real page number TLBLO bits 0...

Page 170: ...formation M Memory coherent TLBLO bit 30 Setting and clearing this bit does not affect memory accesses in the PPC405 In implementations that support multi processing this bit can be used to improve th...

Page 171: ...D value of 0x00 A PID value of 0x00 does not identify a process that can access any page When PID 0x00 a page translation hit only occurs when TID 0x00 It is possible for software to load the TLB with...

Page 172: ...n real mode all address translation and memory protection checks performed by the MMU are disabled After system software initializes the UTLB with page translation entries management of the PPC405 UTL...

Page 173: ...age Exception When instruction address translation is enabled MSR IR 1 an instruction storage exception occurs when access to a page is not permitted for any of the following reasons From user mode Th...

Page 174: ...fetched from a page instead causing an instruction storage interrupt ISI to occur The ISI does not occur when the instruction is fetched but instead occurs when the instruction is executed This preven...

Page 175: ...LO WR only Because this is a privileged instruction access cannot be denied by zone protection dcbz Affected by TLBLO WR and in user mode only ZPR Zn 00 Other cache control instructions can invalidate...

Page 176: ...cause an exception and are instead treated as a no operation dcba Affected by TLBLO WR and in user mode only ZPR Zn 00 dcbt Affected by ZPR Zn 00 in user mode only This instruction is treated as a lo...

Page 177: ...dcbz Data storage interrupt Data storage interrupt dccci Data storage interrupt No violation privileged instruction dcread No violation treated as load No violation privileged instruction icbi No viol...

Page 178: ...sically available Some of the software and data pages must be stored outside physical memory such as on a hard drive when they are not used Ideally the most frequently used pages stay in physical memo...

Page 179: ...also record the information in a separate data structure associated with the page translation entry Page modification information is used to indicate whether an old page can be overwritten with a new...

Page 180: ...he interrupt handler updates the UTLB and returns from the interrupt handler using rfi without enabling virtual mode no additional context synchronization is required However if virtual mode is enable...

Page 181: ...ransfers that occur as a result of an exception An interrupt occurs when the processor suspends execution of a program after detecting an exception The processor saves the suspended program machine st...

Page 182: ...instruction to have completed execution partially completed execution or not have begun execution No instructions following the excepting instruction are executed prior to transferring control to the...

Page 183: ...should be used to reference memory Also one of the following two rules must be followed The memory operand must be aligned on the operand size boundary see Table 2 1 page 353 The accessed memory locat...

Page 184: ...ct when transferring program control to an interrupt handler Alignment 0x0600 Noncritical Synchronous Precise Unaligned operand of dcread lwarx stwcx dcbz to non cacheable or write through memory Prog...

Page 185: ...e return address Refer to the specific interrupt description in Interrupt Reference page 502 for information on the saved return address 2 Save the interrupted program state Figure 7 1 PPC405 Exceptio...

Page 186: ...in real mode Certain interrupts are disabled depending on the exception 6 Synchronize the processor context All interrupts are context synchronizing The processor fetches and executes the first instru...

Page 187: ...though critical and noncritical exceptions use different save restore register pairs simultaneous occurrences of these exceptions are also processed serially The PPC405 uses the interrupt priority sh...

Page 188: ...instruction FPU unavailable Attempted execution of an implemented floating point instruction when MSR FP 0 Not implemented by the PPC405D5 APU unavailable Attempted execution of an implemented auxilia...

Page 189: ...R CE bit is used to enable and disable the interrupt The machine check interrupt can be disabled but the exception is not persistent Machine check exception status is recorded in the machine check int...

Page 190: ...masked All Others No Change Critical input interrupts are enabled or disabled 15 All 0 Reserved 16 EE All 0 External interrupts are disabled masked 17 PR All 0 Processor is in privileged mode 18 FP A...

Page 191: ...n address of 27 0x01B Both registers are read and written using the mfspr and mtspr instructions Save Restore Registers 2 and 3 The save restore registers 2 and 3 SRR2 and SRR3 are 32 bit registers us...

Page 192: ...the EVPR are ignored by the processor The resulting 32 bit exception vector physical address is used by the interrupt mechanism to transfer control to the appropriate interrupt handler Figure 7 4 show...

Page 193: ...ption occurred 6 PTR Program Trap Instruction 0 Did not occur 1 Occurred When set to 1 indicates a successful trap instruction compare occurred resulting in a trap instruction program exception 7 PEU...

Page 194: ...the data access instruction that caused one of the following exceptions Alignment exception Data storage exception Data TLB miss exception Figure 7 6 shows the format of the DEAR register The DEAR is...

Page 195: ...the critical interrupt input signal and forces a critical input interrupt to occur When MSR CE 0 the processor does not recognize the critical interrupt input signal and critical input interrupts cann...

Page 196: ...has saved SRR2 and SRR3 Saving these registers avoids potential corruption of the interrupt handler should another machine check interrupt occur Instruction Machine Check Interrupt Instruction machine...

Page 197: ...the machine check exception SRR3 Loaded with a copy of the MSR at the point the interrupt occurs ESR MCI 1 All remaining bits are cleared to 0 DEAR Not used MSR AP APE WE CE EE PR FP ME FE0 DWE DE FE1...

Page 198: ...depends on the privilege mode In user mode any store or dcbz instruction can cause an exception for this reason No zone protection override can be specified the corresponding zone field value is not e...

Page 199: ...dccci otherwise 0 DIZ 1 if the exception was caused by a zone protection violation otherwise 0 U0F 1 if the exception was caused by a U0 violation otherwise 0 MCI Unchanged All remaining bits are cle...

Page 200: ...an only be specified when instruction virtual mode is enabled MSR IR 1 Non executable addresses have the write executable bit TLBLO EX in the corresponding TLB entry cleared to zero No zone protection...

Page 201: ...cessor recognizes exceptions caused by asserting the noncritical interrupt input signal and forces an external interrupt to occur When MSR EE 0 the processor does not recognize the noncritical interru...

Page 202: ...t is not aligned on a word boundary Executing an stwcx instruction with an operand that is not aligned on a word boundary From privileged mode MSR PR 0 executing a dcread instruction with an operand t...

Page 203: ...e should either Replace the trap instruction with a non trapping instruction Modify the trap conditions to prevent a program interrupt Modify the address in SRR0 to point to the next sequential instru...

Page 204: ...on otherwise 0 This bit is set if software attempts to execute a floating point instruction PPR 1 for attempted execution of a privileged instruction in user mode otherwise 0 PTR 1 for exceptions due...

Page 205: ...of the PowerPC 405 processor Interrupt Classification Noncritical return using the rfi instruction Synchronous Precise Description FPU unavailable exceptions occur when a program attempts to execute a...

Page 206: ...e sc instruction provides a means for a user level program to call a privileged system service routine It is assumed that the appropriate linkage information expected by the system call handler is ini...

Page 207: ...of the PowerPC 405 processor Interrupt Classification Noncritical return using the rfi instruction Synchronous Precise Description APU unavailable exceptions occur when a program attempts to execute a...

Page 208: ...to clear the PIT to 0 does not cause a PIT interrupt This exception is persistent To prevent repeated interrupts from occurring the interrupt handler must clear the exception status in TSR PIS before...

Page 209: ...from occurring the interrupt handler must clear the exception status in TSR FIS before returning This interrupt is enabled only by setting both of the following The FIT interrupt enable bit in the tim...

Page 210: ...og interrupt status bit in the timer status register TSR WIS is cleared to 0 A 0 to 1 transition occurs on the time base bit corresponding to the watchdog time period During the cycle following detect...

Page 211: ...both A TAG field that matches the data effective address page number EA EPN A TID field that matches the current process ID PID Software cannot disable data TLB miss interrupts See TLB Access page 47...

Page 212: ...ruction TLB miss exceptions are associated with the fetching of an instruction from memory However an instruction TLB miss interrupt occurs only if an attempt is made to execute the instruction as req...

Page 213: ...set DBSR IDE This bit is set in addition to other debug status bits When debug interrupts are later enabled the set IDE bit causes a debug interrupt to occur immediately When exiting an interrupt hand...

Page 214: ...effective address of the instruction following the instruction that caused the debug exception EDE Loaded with the 32 bit exception vector physical address of the exception that caused the debug inte...

Page 215: ...er event interrupts A watchdog timer interrupt that provides the ability to set critical interrupts that can aid in recovery from system failures A programmable interval timer interrupt that provides...

Page 216: ...me base The TBU and TBL registers are SPRs with user mode read access and privileged mode write access Reading the time base registers requires use of the move from time base register instruction This...

Page 217: ...ftbu rz Read TBU again cmpw rz rx Check for TBU rollover by comparing old and new bne loop Read the time base again if a rollover occurred Following is a code example for writing the time base simplif...

Page 218: ...presents the number of seconds that have elapsed since the fixed reference time posix_ns A 32 bit variable containing the number of nanoseconds that have elapsed since the last time of day calculation...

Page 219: ...the saved time base value Computing and saving a new value for ticks_per_sec Later calls to compute the time of day can use the updated variables along with the current time base value to calculate t...

Page 220: ...nction Description 0 1 WP Watchdog Period 00 217 clocks 01 221 clocks 10 225 clocks 11 229 clocks Specifies the period for a watchdog timer event 2 3 WRC Watchdog Reset Control 00 No reset 01 Processo...

Page 221: ...rrupt is assigned to exception vector offset 0x1000 Fixed interval timer FIT interrupt This noncritical interrupt is assigned to exception vector offset 0x1010 0 1 2 3 4 5 6 31 ENW WIS WRS PIS FIS Fig...

Page 222: ...l register TCR WP is used to select the TBL bit that controls the time out as shown in Table 8 5 Software cannot disable watchdog time outs This is because the time base register is always incrementin...

Page 223: ...tchdog time out forces a reset if a reset condition is specified by TCR WRC The processor sets the TSR WIS bit but never clears it Only software can clear the bit Figure 8 6 shows the watchdog event s...

Page 224: ...reset watchdog interrupts are disabled because MSR CE 0 However watchdog time outs continue to occur because the time base register is always incrementing and a valid watchdog interval is always spec...

Page 225: ...a valid fixed interval is always specified by TCR FP A FIT event causes a FIT interrupt when both of the following bits are set to 1 The FIT interrupt enable bit in the timer control register TCR FIE...

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Page 227: ...ternal halt signal is de asserted Stop Stop can be used to halt the processor using the JTAG port rather than the external halt signal No instructions are executed during a halt but processor register...

Page 228: ...pping the processor single stepping instruction execution setting breakpoints and monitoring processor status Access to processor resources is provided through the JTAG port External debug events stop...

Page 229: ...from interrupt instruction the processor re enters the stopped state Debug wait mode is enabled by setting the debug wait mode bit in the MSR MSR DWE 1 Internal debug mode and external debug mode must...

Page 230: ...not external debug mode is enabled 1 IDM Internal Debug Mode 0 Disabled 1 Enabled Specifies whether or not internal debug mode is enabled 2 3 RST Reset 00 No reset 01 Processor reset 10 Chip reset 11...

Page 231: ...0 Disabled 1 Enabled Specifies whether or not the instruction address compare 4 IAC4 debug event is enabled 14 IA34 Instruction Address Range Compare 3 4 0 Disabled 1 Enabled Instruction address compa...

Page 232: ...all bits 01 Ignore least significant bit 10 Ignore least significant two bits 11 Ignore least significant five bits Specifies the granularity of DAC2 exact address comparisons 00 Byte granular 01 Half...

Page 233: ...h DV2BE bit corresponds to a byte in the DVC2 register DVC2 events are disabled when DV2BE 0b0000 24 31 Reserved Table 9 2 Debug Control Register 1 DBCR1 Field Definitions Continued Bit Name Function...

Page 234: ...tes whether an IAC2 debug event occurred 7 DR1 Data Address Compare 1 Read Debug Event 0 Did not occur 1 Occurred Indicates whether a DAC1 read debug event occurred 8 DW1 Data Address Compare 1 Write...

Page 235: ...data value compare registers DVC1 and DVC2 These registers are used by the data value compare debug event Figure 9 5 shows the format of the DVCn registers Any data value can be loaded in these regist...

Page 236: ...rigger events are used by external tools to collect instruction trace information Debug status is recorded in the debug status register DBSR A debug event can set debug status bits even if all debug m...

Page 237: ...r than the debug exception Instructions that cause an exception do not result in an IC debug event This sc instruction however causes a system call exception after it executes Here the debug event occ...

Page 238: ...ption handler is executed It is enabled by setting DBCR0 EDE 1 and disabled by clearing DBCR0 EDE 0 The processor reports the occurrence of an EDE debug event by setting the EDE bit in the debug statu...

Page 239: ...that would have executed had the UDE event not occurred Instruction Address Compare Debug Event An instruction address compare IAC debug event occurs immediately before executing an instruction The ef...

Page 240: ...is detected the IAn enable bits in DBCR0 determine which DBSR status bits are set to 1 For example both DBSR IA1 IA2 are set to 1 if DBCR0 IA1 IA2 1 when an IA12 address range match is detected Howeve...

Page 241: ...is in the exclusive IA12 range The processor clears IA12X to 0 The second IAC event occurs when an instruction address is in the inclusive IA12 range The processor sets IA12X to 0 The third IAC event...

Page 242: ...DACn register used in the comparison and the debug status register bit set when the event occurs Any number of DAC exact address match conditions can be enabled simultaneously DAC address range compar...

Page 243: ...by a string instruction In some cases software must use a word size granularity to produce a DAC match on a specific byte address DAC Address Range Match A DAC address range match causes a debug event...

Page 244: ...es that are out of range Table 9 9 summarizes the DBCR1 bits used to control DAC address range comparisons and the DBSR bits used to report their status The processor does not clear the DBSR status bi...

Page 245: ...ed Instructions in this category are dcbf and dcbst Cache control instructions that are speculative are treated as loads by the debug mechanism These instructions can cause DAC read events Instruction...

Page 246: ...page 543 the byte enables specify which DVCn register bytes participate in the DVC comparison DVnBE0 controls participation of DVCn data value byte 0 DVnBE1 controls participation of DVCn data value...

Page 247: ...DBSR status bits are set to reflect the event Read and write DVC events are recorded independently using the DRn and DWn status bits Table 9 12 summarizes how the status bits are used by DVC events St...

Page 248: ...use imprecise debug events when MSR DE 0 Branch taken BT if DBCR0 IDM 0 If internal debug mode is enabled BT events cannot cause imprecise debug events when MSR DE 0 Exception taken EDE Trap instructi...

Page 249: ...wing JTAG Signals The JTAG debug port implements the four required JTAG signals TCK TMS TDI and TDO It also implements the optional TRST signal JTAG Clock The frequency of the JTAG clock signal TCK ca...

Page 250: ...n 11 I HALT Processor halt 12 NC Reserved no connection 13 NC Reserved no connection 14 KEY No pin should be placed at this position 15 NC Reserved no connection 16 GND Ground Notes 1 A 10K pull up re...

Page 251: ...escribe different packages Every pin map within the BSDL description is given a unique name The instruction statements which describe bit patterns that must be shifted into the instruction register to...

Page 252: ...560 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation R...

Page 253: ...at are connected to the same system reset network The scope of a system reset depends on the system implementation The type of reset is recorded in the most recent reset field of the debug status regi...

Page 254: ...reset on the processor state as controlled by the MSR Special Purpose Registers Table 10 2 shows the contents of the special purpose registers SPRs that have defined values following a reset The cont...

Page 255: ...ization code should follow when performing this configuration 1 Configure the real mode memory system by updating the storage attribute control registers After reset all memory is marked as guarded st...

Page 256: ...er is cleared Software should update this register as appropriate to enable instruction caching 4 Configure the data cache to improve data access performance Like the instruction cache the data cache...

Page 257: ...code is presented as pseudocode Where appropriate function calls are given names similar to the PowerPC instruction mnemonics Specific chip level implementations containing the PPC405 might require a...

Page 258: ...errupt handlers Initialize interrupt vector table Initialize exception vector prefix mtspr EVPR prefix_addr Prepare system for asynchronous interrupts Initialize and configure timer resources mtspr PI...

Page 259: ...02 Release www xilinx com 567 Virtex II Pro Platform FPGA Documentation 1 800 255 7778 R Initialize other processor resources Initialize non processor resources Branch to operating system or applicati...

Page 260: ...568 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation R...

Page 261: ...is Shift Right Algebraic Word Immediate Figure 11 1 Instruction Description Format UG011_50_033101 add Add Description The sum of the contents of register rA and register rB is loaded into register rD...

Page 262: ...age 317 Registers Altered A summary of the PowerPC registers that are modified by executing the instruction Exceptions A list of the exceptions that can occur as a result of executing the instruction...

Page 263: ...F is the split field SPRF corresponds to SPRN as follows SPRF0 4 is equivalent to SPRN5 9 SPRF5 9 is equivalent to SPRN0 4 In the mfdcr and mtdcr instructions DCRN is the assembler operand and DCRF is...

Page 264: ...CR CR0 LT GT EQ SO if Rc 1 XER SO OV if OE 1 If an overflow occurs it is possible that the contents of CR0 do not reflect the infinitely precise result Exceptions None Compatibility This instruction i...

Page 265: ...magnitude of the resulting sum Pseudocode rD rA rB if rD 232 1 then XER CA 1 else XER CA 0 Registers Altered rD XER CA CR CR0 LT GT EQ SO if Rc 1 XER SO OV if OE 1 Exceptions None Compatibility This i...

Page 266: ...n be used to perform addition on integers larger than 32 bits as described on page 390 Pseudocode rD rA rB XER CA if rD 232 1 then XER CA 1 else XER CA 0 Registers Altered rD XER CA CR CR0 LT GT EQ SO...

Page 267: ...and added to the contents of register rA The resulting sum is loaded into register rD Simplified mnemonics defined for this instruction are described in the following sections Load Address page 834 Lo...

Page 268: ...D XER CA is updated to reflect the unsigned magnitude of the resulting sum Simplified mnemonics defined for this instruction are described in Subtract Instructions page 831 Pseudocode rD rA EXTS SIMM...

Page 269: ...ng sum addic is one of three instructions that implicitly update CR CR0 without having an RC field The other instructions are andi and andis Simplified mnemonics defined for this instruction are descr...

Page 270: ...sum is loaded into register rD Simplified mnemonics defined for this instruction are described in the following sections Load Immediate page 834 Subtract Instructions page 831 An addis instruction fol...

Page 271: ...ed on page 390 Pseudocode rD rA XER CA 1 if rD 232 1 then XER CA 1 else XER CA 0 Registers Altered rD XER CA CR CR0 LT GT EQ SO if Rc 1 XER SO OV if OE 1 Exceptions None Execution of any of the follow...

Page 272: ...Pseudocode rD rA XER CA if rD 232 1 then XER CA 1 else XER CA 0 Registers Altered rD XER CA CR CR0 LT GT EQ SO if Rc 1 XER SO OV if OE 1 Exceptions None Execution of any of the following invalid instr...

Page 273: ...th the contents of register rB and the result is loaded into register rA Pseudocode rA rS rB Registers Altered rA CR CR0 LT GT EQ SO if Rc 1 Exceptions None Compatibility This instruction is defined b...

Page 274: ...ne s complement of the contents of register rB and the result is loaded into register rA Pseudocode rA rS rB Registers Altered rA CR CR0 LT GT EQ SO if Rc 1 Exceptions None Compatibility This instruct...

Page 275: ...gister rA andi is one of three instructions that implicitly update CR CR0 without having an Rc field The other instructions are addic and andis The andi instruction can be used to test whether any of...

Page 276: ...register rA andis is one of three instructions that implicitly update CR CR0 without having an Rc field The other instructions are addic and andi The andis instruction can be used to test whether any...

Page 277: ...bits If the AA field contains 0 relative addressing the branch instruction address is used as the base address The branch instruction address is the current instruction address CIA If the AA field co...

Page 278: ...ogram flow is transferred to the NIA If the LK field contains 1 then the address of the instruction following the branch instruction CIA 4 is loaded into the LR The BO field specifies whether the bran...

Page 279: ...Pro Platform FPGA Documentation 1 800 255 7778 Alphabetical Instruction Listing R LR if LK 1 Exceptions None Compatibility This instruction is defined by the PowerPC user instruction set architecture...

Page 280: ...is decremented The encoding of the BO field is described in Conditional Branch Control page 367 The BI field specifies which CR bit is tested if the branch is conditional on the CR register Simplifie...

Page 281: ...tform FPGA Documentation 1 800 255 7778 Alphabetical Instruction Listing R the decremented CTR are used as the NIA Compatibility This instruction is defined by the PowerPC user instruction set archite...

Page 282: ...The BO field also specifies whether the CTR is decremented The encoding of the BO field is described in Conditional Branch Control page 367 The BI field specifies which CR bit is tested if the branch...

Page 283: ...91 Virtex II Pro Platform FPGA Documentation 1 800 255 7778 Alphabetical Instruction Listing R Compatibility This instruction is defined by the PowerPC user instruction set architecture UISA It is imp...

Page 284: ...cribed in Compare Instructions page 828 Pseudocode c0 3 0b0000 if rA rB then c0 1 if rA rB then c1 1 if rA rB then c2 1 c3 XER SO n crfD CR CRn c0 3 Registers Altered CR CRn as specified by the crfD f...

Page 285: ...defined for this instruction are described in Compare Instructions page 828 Pseudocode c0 3 0b0000 if rA EXTS SIMM then c0 1 if rA EXTS SIMM then c1 1 if rA EXTS SIMM then c2 1 c3 XER SO n crfD CR CRn...

Page 286: ...are described in Compare Instructions page 828 Pseudocode c0 3 0b0000 if rA rB then c0 1 if rA rB then c1 1 if rA rB then c2 1 c3 XER SO n crfD CR CRn c0 3 Registers Altered CR CRn as specified by th...

Page 287: ...implified mnemonics defined for this instruction are described in Compare Instructions page 828 Pseudocode c0 3 0b0000 if rA 160 UIMM then c0 1 if rA 160 UIMM then c1 1 if rA 160 UIMM then c2 1 c3 XER...

Page 288: ...0 do while n 32 if rS n 1 then leave n n 1 rA n Registers Altered rA CR CR0 LT GT EQ SO if Rc 1 Exceptions None Execution of any of the following invalid instruction forms results in a boundedly undef...

Page 289: ...ecified by crbD Pseudocode CR crbD CR crbA CR crbB Registers Altered CR Exceptions None Execution of any of the following invalid instruction forms results in a boundedly undefined result rather than...

Page 290: ...nto the CR bit specified by crbD Pseudocode CR crbD CR crbA CR crbB Registers Altered CR Exceptions None Execution of any of the following invalid instruction forms results in a boundedly undefined re...

Page 291: ...s defined for this instruction are described in CR Logical Instructions page 828 Pseudocode CR crbD CR crbA CR crbB Registers Altered CR Exceptions None Execution of any of the following invalid instr...

Page 292: ...CR bit specified by crbD Pseudocode CR crbD CR crbA CR crbB Registers Altered CR Exceptions None Execution of any of the following invalid instruction forms results in a boundedly undefined result rat...

Page 293: ...efined for this instruction are described in CR Logical Instructions page 828 Pseudocode CR crbD CR crbA CR crbB Registers Altered CR Exceptions None Execution of any of the following invalid instruct...

Page 294: ...instruction are described in CR Logical Instructions page 828 Pseudocode CR crbD CR crbA CR crbB Registers Altered CR Exceptions None Execution of any of the following invalid instruction forms result...

Page 295: ...into the CR bit specified by crbD Pseudocode CR crbD CR crbA CR crbB Registers Altered CR Exceptions None Execution of any of the following invalid instruction forms results in a boundedly undefined...

Page 296: ...instruction are described in CR Logical Instructions page 828 Pseudocode CR crbD CR crbA CR crbB Registers Altered CR Exceptions None Execution of any of the following invalid instruction forms resul...

Page 297: ...a cacheline is allocated and the value of the bytes in that line are undefined If EA is cachable and has a write through caching policy a no operation occurs This is true whether or not EA is cached b...

Page 298: ...dered a store with respect to data address compare DAC debug exceptions Debug exceptions can occur as a result of executing this instruction Execution of any of the following invalid instruction forms...

Page 299: ...attribute indicates EA is cachable If EA is not cached no operation is performed Pseudocode EA rA 0 rB Flush data cacheline corresponding to EA Registers Altered None Exceptions Data storage if the ac...

Page 300: ...Pro Platform FPGA Documentation Chapter 11 Instruction Set R Compatibility This instruction is defined by the virtual environment architecture level VEA of the PowerPC architecture the PowerPC embedde...

Page 301: ...Pseudocode EA rA 0 rB Invalidate data cacheline corresponding to EA Registers Altered None Exceptions Data storage if the access is prevented by zone protection when data relocation is enabled No acc...

Page 302: ...lowing invalid instruction forms results in a boundedly undefined result rather than a program exception Reserved bits containing a non zero value Compatibility This instruction is defined by the oper...

Page 303: ...peration occurs if the data cacheline is unmodified or if EA is not cached Pseudocode EA rA 0 rB Store modified data cacheline corresponding to EA Registers Altered None Exceptions Data storage if the...

Page 304: ...Pro Platform FPGA Documentation Chapter 11 Instruction Set R Compatibility This instruction is defined by the virtual environment architecture level VEA of the PowerPC architecture the PowerPC embedde...

Page 305: ...m will likely load data from EA in the near future The processor can potentially improve performance by loading the cacheline into the data cache Pseudocode EA rA 0 rB Prefetch data cacheline correspo...

Page 306: ...Pro Platform FPGA Documentation Chapter 11 Instruction Set R Compatibility This instruction is defined by the virtual environment architecture level VEA of the PowerPC architecture the PowerPC embedde...

Page 307: ...oading the cacheline into the data cache In the PPC405 this instruction operates identically to dcbt In other PowerPC implementations this instruction can cause unique bus cycles to occur and addition...

Page 308: ...Pro Platform FPGA Documentation Chapter 11 Instruction Set R Compatibility This instruction is defined by the virtual environment architecture level VEA of the PowerPC architecture the PowerPC embedde...

Page 309: ...eline is allocated and the value of the bytes in that line are cleared to 0 The data cacheline is marked modified If EA is cachable and has a write through caching policy an alignment exception occurs...

Page 310: ...tion is enabled and a valid translation entry corresponding to the EA is not found in the TLB This instruction is considered a store with respect to the above data access exceptions It is also conside...

Page 311: ...chelines it is lost This instruction is intended for use during initialization to invalidate the entire data cache before is enabled A sequence of dccci instructions should be executed one for each co...

Page 312: ...en though the instruction is not address specific multiple addresses are selected by a single EA This instruction does not cause data address compare DAC debug exceptions Execution of any of the follo...

Page 313: ...congruence class If CCR0 CWS 0 the line in way A is selected If CCR0 CWS 1 the line in way B is selected If CCR0 CIS 0 the information read is a word of data from the selected cacheline EA27 29 is use...

Page 314: ...data access exceptions It can cause data TLB miss exceptions related to EA even though the instruction is not address specific multiple addresses are selected by a single EA This instruction cannot ca...

Page 315: ...dividend is negative The 32 bit remainder can be calculated using the following sequence of instructions divw rD rA rB rD quotient mullw rD rD rB rD quotient divisor subf rD rD rA rD remainder The con...

Page 316: ...lease 1 800 255 7778 Virtex II Pro Platform FPGA Documentation Chapter 11 Instruction Set R Compatibility This instruction is defined by the PowerPC user instruction set architecture UISA It is implem...

Page 317: ...rD remainder If Rc 1 CR CR0 LT GT EQ are set using a signed comparison of the result to 0 even though the instruction produces an unsigned integer as a quotient The contents of register rD are undefin...

Page 318: ...struction completion Non memory instructions following eieio can complete before the memory operations ordered by eieio The sync instruction is used to guarantee ordering of both instruction completio...

Page 319: ...nts of register rB A one s complement of the result is calculated and loaded in register rA Pseudocode rA rS rB Registers Altered rA CR CR0 LT GT EQ SO if Rc 1 Exceptions None Compatibility This instr...

Page 320: ...register rA Pseudocode rA EXTS rS24 31 Registers Altered rA CR CR0 LT GT EQ SO if Rc 1 Exceptions None Execution of any of the following invalid instruction forms results in a boundedly undefined resu...

Page 321: ...d into register rA Pseudocode rA EXTS rS16 31 Registers Altered rA CR CR0 LT GT EQ SO if Rc 1 Exceptions None Execution of any of the following invalid instruction forms results in a boundedly undefin...

Page 322: ...f the access is prevented by no access allowed zone protection This only applies to accesses in user mode when data relocation is enabled Data TLB miss if data relocation is enabled and a valid transl...

Page 323: ...Documentation 1 800 255 7778 Alphabetical Instruction Listing R Compatibility This instruction is defined by the virtual environment architecture level VEA of the PowerPC architecture the PowerPC embe...

Page 324: ...the cacheline into the instruction cache Pseudocode EA rA 0 rB Prefetch instruction cacheline corresponding to EA Registers Altered None Exceptions This instruction is considered a load with respect t...

Page 325: ...l Instruction Listing R Compatibility This instruction is defined by the virtual environment architecture level VEA of the PowerPC embedded environment architecture and the PowerPC Book E architecture...

Page 326: ...use during initialization to invalidate the entire instruction cache before is enabled Pseudocode Invalidate the instruction cache Registers Altered None Exceptions Program Attempted execution of thi...

Page 327: ...CCR0 CWS is used to select one of the two cachelines within the congruence class If CCR0 CWS 0 the line in way A is selected If CCR0 CWS 1 the line in way B is selected If CCR0 CIS 0 the information r...

Page 328: ...use data TLB miss exceptions related to the EA even though the instruction is not address specific multiple addresses are selected by a single EA This instruction cannot cause data storage exceptions...

Page 329: ...etes execution Prefetched instructions are discarded by the execution of isync All instructions following isync are executed in the context established by the instructions preceding the isync isync do...

Page 330: ...ress The byte referenced by EA is extended to 32 bits by concatenating 24 0 bits on the left The result is loaded into register rD Pseudocode EA rA 0 EXTS d rD 240 MS EA 1 Registers Altered rD Excepti...

Page 331: ...into register rD The EA is loaded into rA Pseudocode EA rA EXTS d rD 240 MS EA 1 rA EA Registers Altered rA rD Exceptions Data storage if the access is prevented by no access allowed zone protection...

Page 332: ...eudocode EA rA rB rD 240 MS EA 1 rA EA Registers Altered rA rD Exceptions Data storage if the access is prevented by no access allowed zone protection This only applies to accesses in user mode when d...

Page 333: ...s loaded into register rD Pseudocode EA rA 0 rB rD 240 MS EA 1 Registers Altered rD Exceptions Data storage if the access is prevented by no access allowed zone protection This only applies to accesse...

Page 334: ...e used as the base address The halfword referenced by EA is sign extended to 32 bits and loaded into register rD Pseudocode EA rA 0 EXTS d rD EXTS MS EA 2 Registers Altered rD Exceptions Data storage...

Page 335: ...The EA is loaded into rA Pseudocode EA rA EXTS d rD EXTS MS EA 2 rA EA Registers Altered rA rD Exceptions Data storage if the access is prevented by no access allowed zone protection This only applies...

Page 336: ...rD EXTS MS EA 2 rA EA Registers Altered rA rD Exceptions Data storage if the access is prevented by no access allowed zone protection This only applies to accesses in user mode when data relocation is...

Page 337: ...ter rD Pseudocode EA rA 0 rB rD EXTS MS EA 2 Registers Altered rD Exceptions Data storage if the access is prevented by no access allowed zone protection This only applies to accesses in user mode whe...

Page 338: ...memory word are loaded into rD 24 31 Bits 8 15 of the memory word are loaded into rD 16 23 16 0 bits are loaded into rD 0 15 Pseudocode EA rA 0 rB rD 160 MS EA 1 1 MS EA 1 Registers Altered rD Except...

Page 339: ...address The halfword referenced by EA is extended to 32 bits by concatenating 16 0 bits on the left The result is loaded into register rD Pseudocode EA rA 0 EXTS d rD 160 MS EA 2 Registers Altered rD...

Page 340: ...d into register rD The EA is loaded into rA Pseudocode EA rA EXTS d rD 160 MS EA 2 rA EA Registers Altered rA rD Exceptions Data storage if the access is prevented by no access allowed zone protection...

Page 341: ...o rA Pseudocode EA rA rB rD 160 MS EA 2 rA EA Registers Altered rA rD Exceptions Data storage if the access is prevented by no access allowed zone protection This only applies to accesses in user mode...

Page 342: ...s loaded into register rD Pseudocode EA rA 0 rB rD 160 MS EA 2 Registers Altered rD Exceptions Data storage if the access is prevented by no access allowed zone protection This only applies to accesse...

Page 343: ...are loaded into GPRs rD through r31 Pseudocode EA rA 0 EXTS d n rD do while n 31 if n rA n 31 then GPR n MS EA 4 n n 1 EA EA 4 Registers Altered rD through r31 Exceptions Data storage if the access i...

Page 344: ...lease 1 800 255 7778 Virtex II Pro Platform FPGA Documentation Chapter 11 Instruction Set R Compatibility This instruction is defined by the PowerPC user instruction set architecture UISA It is implem...

Page 345: ...tive bytes starting at the memory address referenced by EA are loaded into GPRs rD through RFINAL The sequence of registers wraps around to r0 if necessary RFINAL rD nr 1 modulo 32 Bytes are loaded in...

Page 346: ...miss if data relocation is enabled and a valid translation entry corresponding to the EA is not found in the TLB Execution of any of the following invalid instruction forms results in a boundedly und...

Page 347: ...data n consecutive bytes starting at the memory address referenced by EA are loaded into GPRs rD through RFINAL The sequence of registers wraps around to r0 if necessary RFINAL rD nr 1 modulo 32 Bytes...

Page 348: ...r However a data machine check exception can occur when XER TBC 0 if the following conditions are true The instruction access passes all protection checks The data address is cachable Access of the da...

Page 349: ...or accessing a semaphore See Semaphore Synchronization page 426 for more information Pseudocode EA rA 0 rB rD MS EA 4 RESERVE 1 Registers Altered rD Exceptions Alignment if the EA is not aligned on a...

Page 350: ...into rD 16 23 Bits 16 23 of the memory word are loaded into rD 8 15 Bits 23 31 of the memory word are loaded into rD 0 7 Pseudocode EA rA 0 rB rD MS EA 3 1 MS EA 2 1 MS EA 1 1 MS EA 1 Registers Altere...

Page 351: ...s of register rA are used as the base address The word referenced by EA is loaded into register rD Pseudocode EA rA 0 EXTS d rD MS EA 4 Registers Altered rD Exceptions Data storage if the access is pr...

Page 352: ...to rA Pseudocode EA rA EXTS d rD MS EA 4 rA EA Registers Altered rA rD Exceptions Data storage if the access is prevented by no access allowed zone protection This only applies to accesses in user mod...

Page 353: ...EA Registers Altered rA rD Exceptions Data storage if the access is prevented by no access allowed zone protection This only applies to accesses in user mode when data relocation is enabled Data TLB...

Page 354: ...A rA 0 rB rD MS EA 4 Registers Altered rD Exceptions Data storage if the access is prevented by no access allowed zone protection This only applies to accesses in user mode when data relocation is ena...

Page 355: ...tents of rD are replaced by the low order 32 bits of the temporary result An example of this operation is shown in Figure 3 28 page 408 Pseudocode prod0 31 rA 16 31 rB 0 15 signed temp0 32 prod0 31 rD...

Page 356: ...earest representable value If the result is less than 231 the value stored in rD is 231 If the result is greater than 231 1 the value stored in rD is 231 1 An example of this operation is shown in Fig...

Page 357: ...n rD If the result overflows rD is loaded with the nearest representable value If the result is greater than 232 1 the value stored in rD is 232 1 An example of this operation is shown in Figure 3 28...

Page 358: ...ts of rD are replaced by the low order 32 bits of the temporary result An example of this operation is shown in Figure 3 28 page 408 Pseudocode prod0 31 rA 16 31 rB 0 15 unsigned temp0 32 prod0 31 rD...

Page 359: ...ntents of rD are replaced by the low order 32 bits of the temporary result An example of this operation is shown in Figure 3 29 page 410 Pseudocode prod0 31 rA 0 15 rB 0 15 signed temp0 32 prod0 31 rD...

Page 360: ...earest representable value If the result is less than 231 the value stored in rD is 231 If the result is greater than 231 1 the value stored in rD is 231 1 An example of this operation is shown in Fig...

Page 361: ...in rD If the result overflows rD is loaded with the nearest representable value If the result is greater than 232 1 the value stored in rD is 232 1 An example of this operation is shown in Figure 3 29...

Page 362: ...nts of rD are replaced by the low order 32 bits of the temporary result An example of this operation is shown in Figure 3 29 page 410 Pseudocode prod0 31 rA 0 15 rB 0 15 unsigned temp0 32 prod0 31 rD...

Page 363: ...nts of rD are replaced by the low order 32 bits of the temporary result An example of this operation is shown in Figure 3 30 page 413 Pseudocode prod0 31 rA 16 31 rB 16 31 signed temp0 32 prod0 31 rD...

Page 364: ...rest representable value If the result is less than 231 the value stored in rD is 231 If the result is greater than 231 1 the value stored in rD is 231 1 An example of this operation is shown in Figur...

Page 365: ...rD If the result overflows rD is loaded with the nearest representable value If the result is greater than 232 1 the value stored in rD is 232 1 An example of this operation is shown in Figure 3 30 pa...

Page 366: ...of rD are replaced by the low order 32 bits of the temporary result An example of this operation is shown in Figure 3 30 page 413 Pseudocode prod0 31 rA 16 31 rB 16 31 unsigned temp0 32 prod0 31 rD r...

Page 367: ...fD CR CRn CR CRm Registers Altered CR CRn where n is specified by crfD Exceptions None Execution of any of the following invalid instruction forms results in a boundedly undefined result rather than a...

Page 368: ...CR CRn XER0 3 XER0 3 0b0000 Registers Altered CR CRn where n is specified by the crfD field XER0 3 Exceptions None Execution of any of the following invalid instruction forms results in a boundedly un...

Page 369: ...ode rD CR Registers Altered rD Exceptions None Execution of any of the following invalid instruction forms results in a boundedly undefined result rather than a program exception Reserved bits contain...

Page 370: ...d rD Exceptions Program Attempted execution of this instruction from user mode Execution of any of the following invalid instruction forms results in a boundedly undefined result rather than a program...

Page 371: ...ution of this instruction from user mode Execution of any of the following invalid instruction forms results in a boundedly undefined result rather than a program exception Reserved bits containing a...

Page 372: ...SPRF0 4 rD SPR SPRN Registers Altered rD Exceptions Program Attempted execution of this instruction from user mode if SPRF 0 bit 11 of the instruction opcode is 1 Execution of any of the following in...

Page 373: ...pose Registers page 830 Pseudocode TBRN TBRF5 9 TBRF0 4 rD TBR TBRN Registers Altered rD Exceptions Execution of any of the following invalid instruction forms results in a boundedly undefined result...

Page 374: ...not copied and the corresponding CR bits are unchanged The following table shows the relationship between the CRM field and the rS and CR registers The CRn field is shown for completeness See mtcrf Fi...

Page 375: ...Exceptions None Execution of any of the following invalid instruction forms results in a boundedly undefined result rather than a program exception Reserved bits containing a non zero value Compatibil...

Page 376: ...R DCRN Exceptions Program Attempted execution of this instruction from user mode Execution of any of the following invalid instruction forms results in a boundedly undefined result rather than a progr...

Page 377: ...tion of this instruction from user mode Execution of any of the following invalid instruction forms results in a boundedly undefined result rather than a program exception Reserved bits containing a n...

Page 378: ...SPRF0 4 SPR SPRN rS Registers Altered SPR SPRN Exceptions Program Attempted execution of this instruction from user mode if SPRF 0 bit 11 of the instruction is 1 Execution of any of the following inv...

Page 379: ...f rB The resulting signed 32 bit product is loaded into register rD An example of this operation is shown in Figure 3 34 page 420 Pseudocode rD 0 31 rA 16 31 rB 0 15 signed Registers Altered rD CR CR0...

Page 380: ...The resulting unsigned 32 bit product is loaded into register rD An example of this operation is shown in Figure 3 34 page 420 Pseudocode rD 0 31 rA 16 31 rB 0 15 unsigned Registers Altered rD CR CR0...

Page 381: ...of rB The resulting signed 32 bit product is loaded into register rD An example of this operation is shown in Figure 3 35 page 421 Pseudocode rD 0 31 rA 0 15 rB 0 15 signed Registers Altered rD CR CR0...

Page 382: ...B The resulting unsigned 32 bit product is loaded into register rD An example of this operation is shown in Figure 3 35 page 421 Pseudocode rD 0 31 rA 0 15 rB 0 15 unsigned Registers Altered rD CR CR0...

Page 383: ...quantities This instruction can be used with mullw or mulli to calculate a full 64 bit product Pseudocode prod0 63 rA rB signed rD prod0 31 Registers Altered rD CR CR0 LT GT EQ SO if Rc 1 Exceptions...

Page 384: ...he operands are to be interpreted as signed quantities Pseudocode prod0 63 rA rB unsigned rD prod0 31 Registers Altered rD CR CR0 LT GT EQ SO if Rc 1 Exceptions Execution of any of the following inval...

Page 385: ...rB The resulting signed 32 bit product is loaded into register rD An example of this operation is shown in Figure 3 36 page 422 Pseudocode rD 0 31 rA 16 31 rB 16 31 signed Registers Altered rD CR CR0...

Page 386: ...ulting unsigned 32 bit product is loaded into register rD An example of this operation is shown in Figure 3 36 page 422 Pseudocode rD 0 31 rA 16 31 rB 16 31 unsigned Registers Altered rD CR CR0 LT GT...

Page 387: ...loaded into register rD The result loaded into register rD is always correct regardless of whether the operands are interpreted as signed or unsigned integers This instruction can be used with mulhw t...

Page 388: ...s are interpreted as signed integers The result loaded into register rD is always correct regardless of whether the operands are interpreted as signed or unsigned integers This instruction can be used...

Page 389: ...plement of the result is loaded into register rA The one s complement of a number can be obtained using nand with rS rB Pseudocode rA rS rB Registers Altered rA CR CR0 LT GT EQ SO if Rc 1 Exceptions N...

Page 390: ...de rD rA 1 Registers Altered rD CR CR0 LT GT EQ SO if Rc 1 XER SO OV if OE 1 Exceptions Execution of any of the following invalid instruction forms results in a boundedly undefined result rather than...

Page 391: ...f rD are replaced by the low order 32 bits of the temporary result An example of this operation is shown in Figure 3 31 page 415 Pseudocode prod0 31 rA 16 31 rB 0 15 signed nprod0 31 1 prod0 31 signed...

Page 392: ...epresentable value If the result is less than 231 the value stored in rD is 231 If the result is greater than 231 1 the value stored in rD is 231 1 An example of this operation is shown in Figure 3 31...

Page 393: ...of rD are replaced by the low order 32 bits of the temporary result An example of this operation is shown in Figure 3 32 page 417 Pseudocode prod0 31 rA 0 15 rB 0 15 signed nprod0 31 1 prod0 31 signed...

Page 394: ...epresentable value If the result is less than 231 the value stored in rD is 231 If the result is greater than 231 1 the value stored in rD is 231 1 An example of this operation is shown in Figure 3 32...

Page 395: ...rD are replaced by the low order 32 bits of the temporary result An example of this operation is shown in Figure 3 33 page 419 Pseudocode prod0 31 rA 16 31 rB 16 31 signed nprod0 31 1 prod0 31 signed...

Page 396: ...resentable value If the result is less than 231 the value stored in rD is 231 If the result is greater than 231 1 the value stored in rD is 231 1 An example of this operation is shown in Figure 3 33 p...

Page 397: ...e one s complement of a number can be obtained using nor with rS rB Simplified mnemonics defined for this instruction are described in Other Simplified Mnemonics page 834 Pseudocode rA rS rB Registers...

Page 398: ...ter can be copied into another register using or with rS rB Simplified mnemonics defined for this instruction are described in Other Simplified Mnemonics page 834 Pseudocode rA rS rB Registers Altered...

Page 399: ...e one s complement of the contents of register rB and the result is loaded into register rA Pseudocode rA rS rB Registers Altered rA CR CR0 LT GT EQ SO if Rc 1 Exceptions None Compatibility This instr...

Page 400: ...M field and the result is loaded into register rA Simplified mnemonics defined for this instruction are described in Other Simplified Mnemonics page 834 The preferred no operation an instruction that...

Page 401: ...atenating 16 0 bits on the right The contents of the register rS are ORed with the extended UIMM field and the result is loaded into register rA Pseudocode rA rS UIMM 160 Registers Altered rA Exceptio...

Page 402: ...docode MSR SRR3 Synchronize context NIA SRR2 Registers Altered MSR Exceptions Program Attempted execution of this instruction from user mode Execution of any of the following invalid instruction forms...

Page 403: ...into the MSR Pseudocode MSR SRR1 Synchronize context NIA SRR0 Registers Altered MSR Exceptions Program Attempted execution of this instruction from user mode Execution of any of the following invalid...

Page 404: ...ed data is inserted into register rA under control of the mask If a mask bit contains a 1 the corresponding bit in the rotated data is inserted into the corresponding bit of register rA If a mask bit...

Page 405: ...The contents of register rS are rotated left by the number of bit positions specified by the SH field The rotated data is ANDed with the mask and the result is loaded into register rA This instructio...

Page 406: ...of register rS are rotated left by the number of bit positions specified by the contents of register rB27 31 The rotated data is ANDed with the mask and the result is loaded into register rA This inst...

Page 407: ...truction is context synchronizing Instructions fetched from the NIA use the new context loaded into the MSR Pseudocode SRR1 MSR MSR WE EE PR DR IR 0 SRR0 CIA 4 Synchronize context NIA EVPR0 15 0x0C00...

Page 408: ...are lost and 0 bits fill vacated bit positions on the right The result is loaded into register rA If rB26 1 register rA is cleared to zero Pseudocode n rB 27 31 r ROTL rS n if rB 26 0 then m MASK 0 3...

Page 409: ...ded into register rA If rS contains a negative number and any 1 bits are shifted out of the least significant bit position XER CA is set to 1 Otherwise XER CA is cleared to 0 If rB26 1 XER CA and all...

Page 410: ...d bit positions on the left The result is loaded into register rA If rS contains a negative number and any 1 bits are shifted out of the least significant bit position XER CA is set to 1 Otherwise XER...

Page 411: ...bit are lost and 0 bits fill the vacated bit positions on the left The result is loaded into register rA If rB26 1 register rA is cleared to 0 Pseudocode n rB 27 31 r ROTL rS 32 n if rB 26 0 then m M...

Page 412: ...cant byte of register rS is stored into the byte referenced by EA Pseudocode EA rA 0 EXTS d MS EA 1 rS 24 31 Registers Altered None Exceptions Data storage if the access is prevented by zone protectio...

Page 413: ...EXTS d MS EA 1 rS 24 31 rA EA Registers Altered rA Exceptions Data storage if the access is prevented by zone protection when data relocation is enabled No access allowed zone protection applies only...

Page 414: ...rA Exceptions Data storage if the access is prevented by zone protection when data relocation is enabled No access allowed zone protection applies only to accesses in user mode Read only zone protecti...

Page 415: ...Registers Altered None Exceptions Data storage if the access is prevented by zone protection when data relocation is enabled No access allowed zone protection applies only to accesses in user mode Rea...

Page 416: ...nt halfword of register rS is stored into the halfword referenced by EA Pseudocode EA rA 0 EXTS d MS EA 2 rS 16 31 Registers Altered None Exceptions Data storage if the access is prevented by zone pro...

Page 417: ...d into the byte referenced by EA 1 Pseudocode EA rA 0 rB MS EA 2 rS 24 31 rS 16 23 Registers Altered None Exceptions Data storage if the access is prevented by zone protection when data relocation is...

Page 418: ...rA EXTS d MS EA 2 rS 16 31 rA EA Registers Altered rA Exceptions Data storage if the access is prevented by zone protection when data relocation is enabled No access allowed zone protection applies o...

Page 419: ...Altered rA Exceptions Data storage if the access is prevented by zone protection when data relocation is enabled No access allowed zone protection applies only to accesses in user mode Read only zone...

Page 420: ...31 Registers Altered None Exceptions Data storage if the access is prevented by zone protection when data relocation is enabled No access allowed zone protection applies only to accesses in user mode...

Page 421: ...d into n consecutive words starting at the memory address referenced by EA Pseudocode EA rA 0 EXTS d r rS do while r 31 MS EA 4 GPR r r r 1 EA EA 4 Registers Altered None Exceptions Data storage if th...

Page 422: ...4 GPRs rS through rS nr 1 are stored into n consecutive bytes starting at the memory address referenced by EA The sequence of registers wraps around to r0 if necessary The bytes within each register...

Page 423: ...ivileged modes Data TLB miss if data relocation is enabled and a valid translation entry corresponding to the EA is not found in the TLB Execution of any of the following invalid instruction forms res...

Page 424: ...TBC Let nr specify the number of registers to load with data nr CEIL n 4 GPRs rS through rS nr 1 are stored into n consecutive bytes starting at the memory address referenced by EA The sequence of re...

Page 425: ...C 0 data storage and data TLB miss exceptions do not occur However a data machine check exception can occur when XER TBC 0 if the following conditions are true The instruction access passes all protec...

Page 426: ...tents of register rS are stored into the word referenced by EA Pseudocode EA rA 0 EXTS d MS EA 4 rS Registers Altered None Exceptions Data storage if the access is prevented by zone protection when da...

Page 427: ...are stored into the byte referenced by EA 1 rS 8 15 are stored into the byte referenced by EA 2 rS 0 7 are stored into the byte referenced by EA 3 Pseudocode EA rA 0 rB MS EA 4 rS 24 31 rS 16 23 rS 8...

Page 428: ...lease 1 800 255 7778 Virtex II Pro Platform FPGA Documentation Chapter 11 Instruction Set R Compatibility This instruction is defined by the PowerPC user instruction set architecture UISA It is implem...

Page 429: ...vation bit is cleared to 0 when the instruction is executed no store operation is performed Execution of this instruction always clears the reservation bit CR CR0 is updated as follows CR CR0 LT GT ar...

Page 430: ...enabled No access allowed zone protection applies only to accesses in user mode Read only zone protection applies to user and privileged modes Data TLB miss if data relocation is enabled and a valid...

Page 431: ...TS d MS EA 4 rS rA EA Registers Altered rA Exceptions Data storage if the access is prevented by zone protection when data relocation is enabled No access allowed zone protection applies only to acces...

Page 432: ...ons Data storage if the access is prevented by zone protection when data relocation is enabled No access allowed zone protection applies only to accesses in user mode Read only zone protection applies...

Page 433: ...Altered None Exceptions Data storage if the access is prevented by zone protection when data relocation is enabled No access allowed zone protection applies only to accesses in user mode Read only zon...

Page 434: ...rB to the one s complement of register rA and adding 1 to the result Simplified mnemonics defined for this instruction are described in Subtract Instructions page 831 Pseudocode rD rA rB 1 Registers A...

Page 435: ...g 1 to the result XER CA is updated to reflect the unsigned magnitude of the result Simplified mnemonics defined for this instruction are described in Subtract Instructions page 831 Pseudocode rD rA r...

Page 436: ...e subtract from extended instructions can be used to perform subtraction on integers larger than 32 bits as described on page 392 Pseudocode rD rA rB XER CA if rD 232 1 then XER CA 1 else XER CA 0 Reg...

Page 437: ...operation is equivalent to adding the contents of the SIMM field sign extended to 32 bits to the one s complement of register rA and adding 1 to the result XER CA is updated to reflect the unsigned ma...

Page 438: ...than 32 bits as described on page 392 Pseudocode rD rA 0xFFFF_FFFF XER CA if rD 232 1 then XER CA 1 else XER CA 0 Registers Altered rD XER CA CR CR0 LT GT EQ SO if Rc 1 XER SO OV if OE 1 Exceptions Ex...

Page 439: ...escribed on page 392 Pseudocode rD rA XER CA if rD 232 1 then XER CA 1 else XER CA 0 Registers Altered rD XER CA CR CR0 LT GT EQ SO if Rc 1 XER SO OV if OE 1 Exceptions Execution of any of the followi...

Page 440: ...antee ordering of both instruction completion and storage access The eieio instruction orders memory access not instruction completion Non memory instructions following eieio can complete before the m...

Page 441: ...follow the tlbia instruction to guarantee that the effect of invalidating the TLB is visible to subsequent instructions Registers Altered None Exceptions Program Attempted execution of this instructio...

Page 442: ...s read regardless of whether address translation is enabled Simplified mnemonics defined for this instruction are described in TLB Management Instructions page 832 Pseudocode tlb_entry rA26 31 if WS4...

Page 443: ...com 751 Virtex II Pro Platform FPGA Documentation 1 800 255 7778 Alphabetical Instruction Listing R architecture Because it is optional and not defined by the PowerPC architecture it is not implement...

Page 444: ...PID24 31 If a valid entry is found the corresponding TLB index is loaded into rD The TLB is searched regardless of whether address translation is enabled If Rc 1 CR CR0 is updated to reflect the sear...

Page 445: ...n Listing R Compatibility This instruction is defined as optional by the operating environment architecture level OEA of the PowerPC embedded environment architecture and the PowerPC Book E architectu...

Page 446: ...Registers Altered None Exceptions Program Attempted execution of this instruction from user mode Execution of any of the following invalid instruction forms results in a boundedly undefined result ra...

Page 447: ...ronizing instruction should follow the tlbwe instruction to guarantee that the effect of writing a TLB entry is visible to subsequent instructions Simplified mnemonics defined for this instruction are...

Page 448: ...002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation Chapter 11 Instruction Set R architecture Because it is optional and not defined by the PowerPC architecture it is not implemented...

Page 449: ...eptions are disabled MSR DE 0 an imprecise debug event is reported by setting DBSR IDE to 1 If the trap instruction debug event is enabled as an internal debug event DBCR TDE 1 DBCR IDM 1 and DBCR EDM...

Page 450: ...Execution of any of the following invalid instruction forms results in a boundedly undefined result rather than a program exception Reserved bits containing a non zero value Compatibility This instruc...

Page 451: ...1 and debug exceptions are disabled MSR DE 0 an imprecise debug event is reported by setting DBSR IDE to 1 If the trap instruction debug event is enabled as an internal debug event DBCR TDE 1 DBCR IDM...

Page 452: ...Execution of any of the following invalid instruction forms results in a boundedly undefined result rather than a program exception Reserved bits containing a non zero value Compatibility This instruc...

Page 453: ...instruction from user mode Execution of any of the following invalid instruction forms results in a boundedly undefined result rather than a program exception Reserved bits containing a non zero value...

Page 454: ...tion from user mode Execution of any of the following invalid instruction forms results in a boundedly undefined result rather than a program exception Reserved bits containing a non zero value Compat...

Page 455: ...th the contents of register rB and the result is loaded into register rA Pseudocode rA rS rB Registers Altered rA CR CR0 LT GT EQ SO if Rc 1 Exceptions None Compatibility This instruction is defined b...

Page 456: ...ating 16 0 bits on the left The contents of register rS are XORed with the extended UIMM field and the result is loaded into register rA Pseudocode rA rS 160 UIMM Registers Altered rA Exceptions None...

Page 457: ...ncatenating 16 0 bits on the right The contents of register rS are XORed with the extended UIMM field and the result is loaded into register rA Pseudocode rA rS UIMM 160 Registers Altered rA Exception...

Page 458: ...766 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation Chapter 11 Instruction Set R...

Page 459: ...Registers GPRs page 360 CR Condition Register Condition Register CR page 361 MSR Machine State Register Machine State Register page 431 CCR0 Core Configuration Register 0 Core Configuration Register...

Page 460: ...GR page 455 SLER Storage Little Endian Register Storage Little Endian Register SLER page 455 SPRG0 SPR General Purpose Register 0 SPR General Purpose Registers page 432 SPRG1 SPR General Purpose Regis...

Page 461: ...l Purpose Register 13 13 0x0D 0b01101 No Read Write Undefined r14 General Purpose Register 14 14 0x0E 0b01110 No Read Write Undefined r15 General Purpose Register 15 15 0x0F 0b01111 No Read Write Unde...

Page 462: ...ble Yes Read Write 0x0000_0000 Table A 4 Special Purpose Registers Sorted by Name Name Descriptive Name SPRN SPRF Privileged Access Reset Value Dec Hex Hex Binary CCR0 Core Configuration Register 0 94...

Page 463: ...01000 No Read Only Undefined SPRG4 SPR General Purpose Register 4 276 0x114 0x288 0b10100_01000 Yes Read Write Undefined SPRG5 SPR General Purpose Register 5 261 0x105 0x0A8 0b00101_01000 No Read Only...

Page 464: ...277 0x115 0x2A8 0b10101_01000 Yes Read Write Undefined SPRG6 SPR General Purpose Register 6 278 0x116 0x2C8 0b10110_01000 Yes Read Write Undefined SPRG7 SPR General Purpose Register 7 279 0x117 0x2E8...

Page 465: ...0x3FB 0x37F 0b11011_11111 Yes Read Write 0x0000_0000 Table A 5 Special Purpose Registers Sorted by SPRN Continued Name Descriptive Name SPRN SPRF Privileged Access Reset Value Dec Hex Hex Binary Table...

Page 466: ...101 Yes Read Write Undefined DAC2 Data Address Compare 2 1015 0x3F7 0x2FF 0b10111_11111 Yes Read Write Undefined TSR Timer Status Register 984 0x3D8 0x31E 0b11000_11110 Yes Read Clear Undefined1 SGR S...

Page 467: ...BRN that appears in the instruction encoding Device Control Registers Device control registers DCRs are not architecturally part of the PPC405 DCRs are used to control configure and record status for...

Page 468: ...776 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation Appendix A Register Summary R...

Page 469: ...by Mnemonic Table B 1 lists the PPC405 instruction set in alphabetical order by mnemonic Table B 1 Instructions Sorted by Mnemonic 0 6 9 11 12 14 16 17 20 21 22 26 30 31 add 31 rD rA rB OE 266 Rc add...

Page 470: ...31 00000 rA rB 278 0 dcbtst 31 00000 rA rB 246 0 dcbz 31 00000 rA rB 1014 0 dccci 31 00000 rA rB 454 0 dcread 31 rD rA rB 486 0 divw 31 rD rA rB OE 491 Rc divwu 31 rD rA rB OE 459 Rc eieio 31 00000 00...

Page 471: ...rD rA rB OE 140 Rc machhw 4 rD rA rB OE 44 Rc machhws 4 rD rA rB OE 108 Rc machhwsu 4 rD rA rB OE 76 Rc machhwu 4 rD rA rB OE 12 Rc maclhw 4 rD rA rB OE 428 Rc maclhws 4 rD rA rB OE 492 Rc maclhwsu 4...

Page 472: ...rA rB OE 110 Rc nmaclhw 4 rD rA rB OE 430 Rc nmaclhws 4 rD rA rB OE 494 Rc nor 31 rS rA rB 124 Rc or 31 rS rA rB 444 Rc orc 31 rS rA rB 412 Rc ori 24 rS rA UIMM oris 25 rS rA UIMM rfci 19 00000 00000...

Page 473: ...stwux 31 rS rA rB 183 0 stwx 31 rS rA rB 151 0 subf 31 rD rA rB OE 40 Rc subfc 31 rD rA rB OE 8 Rc subfe 31 rD rA rB OE 136 Rc subfic 8 rD rA SIMM subfme 31 rD rA 00000 OE 232 Rc subfze 31 rD rA 0000...

Page 474: ...rB OE 140 Rc mulchw 4 rD rA rB 168 Rc macchw 4 rD rA rB OE 172 Rc nmacchw 4 rD rA rB OE 174 Rc macchwsu 4 rD rA rB OE 204 Rc macchws 4 rD rA rB OE 236 Rc nmacchws 4 rD rA rB OE 238 Rc mullhwu 4 rD rA...

Page 475: ...O BI 00000 528 LK rlwimi 20 rS rA SH MB ME Rc rlwinm 21 rS rA SH MB ME Rc rlwnm 23 rS rA rB MB ME Rc ori 24 rS rA UIMM oris 25 rS rA UIMM xori 26 rS rA UIMM xoris 27 rS rA UIMM andi 28 rS rA UIMM andi...

Page 476: ...000 00000 E 0000 163 0 stwux 31 rS rA rB 183 0 subfze 31 rD rA 00000 OE 200 Rc addze 31 rD rA 00000 OE 202 Rc stbx 31 rS rA rB 215 0 subfme 31 rD rA 00000 OE 232 Rc addme 31 rD rA 00000 OE 234 Rc mull...

Page 477: ...rA rB 536 Rc tlbsync 31 00000 00000 00000 566 0 lswi 31 rD rA NB 597 0 sync 31 00000 00000 00000 598 0 stswx 31 rS rA rB 661 0 stwbrx 31 rS rA rB 662 0 stswi 31 rS rA NB 725 0 dcba 31 00000 rA rB 758...

Page 478: ...rA d lhau 43 rD rA d sth 44 rS rA d sthu 45 rS rA d lmw 46 rD rA d stmw 47 rS rA d Table B 2 Instructions Sorted by Opcode Continued 0 6 9 11 12 14 16 17 20 21 22 26 30 31 Table B 3 Integer Add and Su...

Page 479: ...rB 392 Rc mulli 7 rD rA SIMM mullw 31 rD rA rB OE 235 Rc Table B 5 Integer Multiply Accumulate Instructions 0 6 11 16 21 22 31 macchw 4 rD rA rB OE 172 Rc macchws 4 rD rA rB OE 236 Rc macchwsu 4 rD rA...

Page 480: ...1 rS rA rB 60 Rc andi 28 rS rA UIMM andis 29 rS rA UIMM cntlzw 31 rS rA 00000 26 Rc eqv 31 rS rA rB 284 Rc extsb 31 rS rA 00000 954 Rc extsh 31 rS rA 00000 922 Rc nand 31 rS rA rB 476 Rc nor 31 rS rA...

Page 481: ...rD rA rB 119 0 lbzx 31 rD rA rB 87 0 lha 42 rD rA d lhau 43 rD rA d lhaux 31 rD rA rB 375 0 lhax 31 rD rA rB 343 0 lhz 40 rD rA d lhzu 41 rD rA d lhzux 31 rD rA rB 311 0 lhzx 31 rD rA rB 279 0 lwz 32...

Page 482: ...ad and Store String Instructions 0 6 11 16 21 31 lswi 31 rD rA NB 597 0 lswx 31 rD rA rB 533 0 stswi 31 rS rA NB 725 0 stswx 31 rS rA rB 661 0 Table B 15 Branch Instructions 0 6 11 16 21 30 31 b 18 LI...

Page 483: ...ynchronization Instructions 0 6 11 16 21 31 eieio 31 00000 00000 00000 854 0 isync 19 00000 00000 00000 150 0 lwarx 31 rD rA rB 20 0 stwcx 31 rS rA rB 150 1 sync 31 00000 00000 00000 598 0 Table B 20...

Page 484: ...0 rA rB 470 0 dcbst 31 00000 rA rB 54 0 dcbt 31 00000 rA rB 278 0 dcbtst 31 00000 rA rB 246 0 dcbz 31 00000 rA rB 1014 0 dccci 31 00000 rA rB 454 0 dcread 31 rD rA rB 486 0 icbi 31 00000 rA rB 982 0 i...

Page 485: ...A UIMM andi 28 rS rA UIMM andis 29 rS rA UIMM lwz 32 rD rA d lwzu 33 rD rA d lbz 34 rD rA d lbzu 35 rD rA d stw 36 rS rA d stwu 37 rS rA d stb 38 rS rA d stbu 39 rS rA d lhz 40 rD rA d lhzu 41 rD rA d...

Page 486: ...4 0 mfcr 31 rD 00000 00000 19 0 lwarx 31 rD rA rB 20 0 lwzx 31 rD rA rB 23 0 slw 31 rS rA rB 24 Rc cntlzw 31 rS rA 00000 26 Rc and 31 rS rA rB 28 Rc cmpl 31 crfD 00 rA rB 32 0 dcbst 31 00000 rA rB 54...

Page 487: ...31 rS rA rB 476 Rc dcread 31 rD rA rB 486 0 mcrxr 31 crfD 00 00000 00000 512 0 lswx 31 rD rA rB 533 0 lwbrx 31 rD rA rB 534 0 srw 31 rS rA rB 536 Rc tlbsync 31 00000 00000 00000 566 0 lswi 31 rD rA N...

Page 488: ...ble B 30 XL Form 0 6 9 11 14 16 21 31 mcrf 19 crfD 00 crfS 00 00000 0 0 bclr 19 BO BI 00000 16 LK crnor 19 crbD crbA crbB 33 0 rfi 19 00000 00000 00000 50 0 rfci 19 00000 00000 00000 51 0 crandc 19 cr...

Page 489: ...36 Rc nmacchws 4 rD rA rB OE 238 Rc maclhwu 4 rD rA rB OE 396 Rc maclhw 4 rD rA rB OE 428 Rc nmaclhw 4 rD rA rB OE 430 Rc maclhwsu 4 rD rA rB OE 460 Rc maclhws 4 rD rA rB OE 492 Rc nmaclhws 4 rD rA rB...

Page 490: ...x x x UISA D addic x x x UISA D addic x x x UISA D addis x x x UISA D addme x x x UISA XO addze x x x UISA XO and x x x UISA X andc x x x UISA X andi x x x UISA D andis x x x UISA D b x x x UISA I bc...

Page 491: ...x x x UISA D lbzu x x x UISA D lbzux x x x UISA X lbzx x x x UISA X lha x x x UISA D lhau x x x UISA D lhaux x x x UISA X lhax x x x UISA X lhbrx x x x UISA X lhz x x x UISA D lhzu x x x UISA D lhzux...

Page 492: ...ISA X mfcr x x x UISA X mfdcr x x OEA x XFX mfmsr x x x OEA x X mfspr x x x UISA XFX OEA x1 mftb x x VEA XFX mtcrf x x x UISA XFX mtdcr x x OEA x XFX mtmsr x x x OEA x X mtspr x x x UISA XFX OEA x1 mu...

Page 493: ...imi x x x UISA M rlwinm x x x UISA M rlwnm x x x UISA M sc x x x UISA SC slw x x x UISA X sraw x x x UISA X srawi x x x UISA X srw x x x UISA X stb x x x UISA D stbu x x x UISA D stbux x x x UISA X st...

Page 494: ...lified mnemonic its equivalent mnemonic is listed in the column headed Equivalent Mnemonic Otherwise the column is shaded gray stwbrx x x x UISA X stwcx x x x UISA X stwu x x x UISA D stwux x x x UISA...

Page 495: ...page 576 addic Add Immediate Carrying and Record page 577 addis Add Immediate Shifted page 578 addme Add to Minus One Extended page 579 addme Add to Minus One Extended and Record addmeo Add to Minus O...

Page 496: ...CTR Not Zero to Link Register bclr page 823 bdnzlrl Branch if Decremented CTR Not Zero to Link Register and Link bclrl page 824 bdnzt Branch if Decremented CTR Not Zero and Condition True bc page 822...

Page 497: ...827 bf Branch if Condition False bc page 822 bfa Branch if Condition False Absolute bca page 822 bfctr Branch if Condition False to Count Register bcctr page 823 bfctrl Branch if Condition False to C...

Page 498: ...ess Than bc page 825 blta Branch if Less Than Absolute bca page 825 bltctr Branch if Less Than to Count Register bcctr page 826 bltctrl Branch if Less Than to Count Register and Link bcctrl page 827 b...

Page 499: ...verflow and Link bcl page 826 bnsla Branch if Not Summary Overflow Absolute and Link bcla page 826 bnslr Branch if Not Summary Overflow to Link Register bclr page 826 bnslrl Branch if Not Summary Over...

Page 500: ...ister AND page 597 crandc Condition Register AND with Complement page 598 crclr Condition Register Clear crxor page 828 creqv Condition Register Equivalent page 599 crmove Condition Register Move cror...

Page 501: ...nd Record rlwinm extsb Extend Sign Byte page 628 extsb Extend Sign Byte and Record extsh Extend Sign Halfword page 629 extsh Extend Sign Halfword and Record icbi Instruction Cache Block Invalidate pag...

Page 502: ...Modulo Signed with Overflow Enabled macchwo Multiply Accumulate Cross Halfword to Word Modulo Signed with Overflow Enabled and Record macchws Multiply Accumulate Cross Halfword to Word Saturate Signed...

Page 503: ...Enabled machhwuo Multiply Accumulate High Halfword to Word Modulo Unsigned with Overflow Enabled and Record maclhw Multiply Accumulate Low Halfword to Word Modulo Signed page 671 maclhw Multiply Accu...

Page 504: ...ss Register mfdvc1 Move From Data Value Compare 1 mfdvc2 Move From Data Value Compare 2 mfesr Move From Exception Syndrome Register mfevpr Move From Exception Vector Prefix Register mfiac1 Move From I...

Page 505: ...age 681 mftbl Move From Time Base Lower mfspr page 830 mftbu Move From Time Base Upper mftcr Move From Timer Control Register mftsr Move From Timer Status Register mfusprg0 Move From User SPR General...

Page 506: ...rogrammable Interval Timer mtsgr Move to Storage Guarded Register mtsler Move to Storage Little Endian Register mtspr Move to Special Purpose Register page 686 mtsprg0 Move to SPR General Purpose Regi...

Page 507: ...mulhhwu Multiply High Halfword to Word Unsigned and Record mulhw Multiply High Word page 691 mulhw Multiply High Word and Record mulhwu Multiply High Word Unsigned page 692 mulhwu Multiply High Word...

Page 508: ...ow Enabled and Record nmachhws Negative Multiply Accumulate High Halfword to Word Saturate Signed page 702 nmachhws Negative Multiply Accumulate High Halfword to Word Saturate Signed and Record nmachh...

Page 509: ...29 rotlw Rotate Left and Record rlwinm rotlwi Rotate Left Immediate rlwinm rotlwi Rotate Left Immediate and Record rlwinm rotrwi Rotate Right Immediate rlwinm rotrwi Rotate Right Immediate and Record...

Page 510: ...act Carrying and Record subfc subco Subtract Carrying with Overflow Enabled subfco page 832 subco Subtract Carrying with Overflow Enabled and Record subfco subf Subtract from page 742 subf Subtract fr...

Page 511: ...Enabled and Record subfo sync Synchronize page 748 tlbia TLB Invalidate All page 749 tlbre TLB Read Entry page 750 tlbrehi Read TLBHI Portion of TLB Entry tlbre page 832 tlbrelo Read TLBLO Portion of...

Page 512: ...te twi twlng Trap if Logically Not Greater Than tw twlngi Trap if Logically Not Greater Than Immediate twi twlnl Trap if Logically Not Less Than tw twlnli Trap if Logically Not Less Than Immediate twi...

Page 513: ...met The condition tested can include a specific bit b in the CR whether or not the contents of the CTR are zero or both The simplified mnemonics in Table C 2 through Table C 6 are formed using the fo...

Page 514: ...nt CTR Branch if CTR 0 bdz bdza bdzlr bdzl bdzla bdzlrl Decrement CTR Branch if CTR 0 and Condition True CRb 1 bdzt bdzta bdztlr bdztl bdztla bdztlrl Decrement CTR Branch if CTR 0 and Condition False...

Page 515: ...bdnztlr b bclr 8 b Decrement CTR Branch if CTR 0 and Condition False CRb 0 bdnzflr b bclr 0 b Decrement CTR Branch if CTR 0 bdzlr bclr 18 0 Decrement CTR Branch if CTR 0 and Condition True CRb 1 bdztl...

Page 516: ...lse CRb 0 bdzfl b target bcl 2 b target bdzfla b target bcla 2 b target Table C 5 Branch True False to Relative Absolute LK 1 Continued Operation LR Updated Branch Relative Branch Absolute Simplified...

Page 517: ...ns Operation LR not Updated LR Updated Relative Absolute to LR to CTR Relative Absolute to LR to CTR Table C 9 Table C 10 Table C 11 Table C 12 Branch if Less Than blt blta bltlr bltctr bltl bltla blt...

Page 518: ...son to Relative Absolute LK 0 Continued Operation LR not Updated Branch Relative Branch Absolute Simplified Mnemonic Equivalent Mnemonic Simplified Mnemonic Equivalent Mnemonic Table C 10 Branch Compa...

Page 519: ...target Branch if Not Equal bnel n target bcl 4 4 n 2 target bnela n target bcla 4 4 n 2 target Branch if Not Greater Than bngl n target bcl 4 4 n 1 target bngla n target bcla 4 4 n 1 target Branch if...

Page 520: ...o 1 A suffix clears the y bit to 0 Compare Instructions The PowerPC compare instructions include an L opcode field that specifies whether the comparison is performed on a word or doubleword operand In...

Page 521: ...rray index by the width of an element Condition Register Clear crclr bx crxor bx bx bx Condition Register Move crmove bx by cror bx by by Condition Register Not crnot bx by crnor bx by by Table C 14 S...

Page 522: ...mtdac1 rS mtspr 1014 rS mfdac1 rD mfspr rD 1014 Data Address Compare 2 mtdac2 rS mtspr 1015 rS mfdac2 rD mfspr rD 1015 Debug Control Register 0 mtdbcr0 rS mtspr 1010 rS mfdbcr0 rD mfspr rD 1010 Debug...

Page 523: ...General Purpose Register 5 mtsprg5 rS mtspr 277 rS SPR General Purpose Register 6 mfsprg6 rD mfspr rD 262 SPR General Purpose Register 6 mtsprg6 rS mtspr 278 rS SPR General Purpose Register 7 mfsprg7...

Page 524: ...ison and the column headed U indicates an unsigned greater than comparison Table C 17 Simplified Mnemonics for Subtract Instructions Operation Simplified Mnemonic Equivalent Mnemonic Subtract rA rB su...

Page 525: ...Mnemonic Trap if less than twlt rA rB tw 16 rA rB twlti rA SIMM twi 16 rA SIMM Trap if less than or equal twle rA rB tw 20 rA rB twlei rA SIMM twi 20 rA SIMM Trap if equal tweq rA rB tw 4 rA rB tweqi...

Page 526: ...ress syntax d rA Move Register The simplified mnemonics in Table C 24 provide a shorthand for moving the contents of a GPR to another GPR Complement Register The simplified mnemonics in Table C 25 pro...

Page 527: ...s a shorthand for copying the contents of a GPR into the CR Table C 25 Simplified Mnemonics for Complement Register Operation Simplified Mnemonic Equivalent Mnemonic Complement Not Register not rA rS...

Page 528: ...836 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation Appendix C Simplified Mnemonics R...

Page 529: ...g on an lwarx instruction that fails to return a desired value Performance can also be improved by using an ordinary load instruction to do the initial value check as follows loop lwz r5 0 r3 load the...

Page 530: ...d into r5 loop lwarx r5 0 r3 load and reserve stwcx r4 0 r3 store new value if still reserved bne loop loop if reservation lost Fetch and Add The fetch and add primitive atomically increments a memory...

Page 531: ...r6 were not equal by exiting the primitive with CR0 EQ 0 If this indication is not required by the application the second bne can be omitted The mr is used only when the application requires that the...

Page 532: ...ress is in r4 and the next element pointers are at offset zero in the respective element data structure It is also assumed that the next element pointer of each list element is in a reservation granul...

Page 533: ...ft amount Shift left immediate n 3 shift amount 32 rlwinm r2 r2 sh 0 31 sh rlwimi r2 r3 sh 32 sh 31 rlwinm r3 r3 sh 0 31 sh rlwimi r3 r4 sh 32 sh 31 rlwinm r4 r4 sh 0 31 sh Shift left n 2 shift amount...

Page 534: ...tions and the instruction timings and latencies Usually the implementation involves a combination of conditional branches and unconditional branches Conditional branches require the evaluation of cond...

Page 535: ...structions that can benefit from this action are Integer arithmetic compare and logical instructions that have the Rc opcode field set The addic andi and andis instructions CR logical instructions The...

Page 536: ...s includes PLB contention between the instruction and data caches and the time associated with performing cache line fills and flushes Unless stated otherwise the number of cycles described applies to...

Page 537: ...ion occurs If the instruction is predicted early at or before prefetch it executes in one cycle If the instruction is predicted during decode it executes in two cycles If the prediction is incorrect t...

Page 538: ...uction that uses the loaded data a load use dependency exists When the loaded data is available it is forwarded to the operand register of the dependent instruction This prevents a processor stall fro...

Page 539: ...bytes are not aligned on a word boundary Access to intermediate bytes consume one cycle for each word accessed Access to trailing bytes consume one cycle Unused bytes are discarded if the trailing by...

Page 540: ...isses Cacheable instruction fetch misses and non cacheable instruction fetches incur penalty cycles for accessing memory over the PLB These penalty cycles depend on the speed of the PLB and when the a...

Page 541: ...tions is usually limited to the operating system kernel and other privileged mode software Applications usually require no modification Software porting can be simplified through the use of structured...

Page 542: ...ntrol Register TSR Timer Status Register DACn Data address compare registers Debugging DBCRn Debug control registers DBSR Debug status register DVCn Data value compare registers IACn Instruction addre...

Page 543: ...e control register THRMn Thermal assist unit registers Thermal management Table E 2 6xx 7xx Registers Not Supported by 40x Processors Name Description Purpose Table E 3 Comparison of MSR Bit Definitio...

Page 544: ...late a 52 bit virtual address within a page to a 32 bit physical address The page translation tables are created by software and stored in system memory The processor uses a translation look aside buf...

Page 545: ...entries Zone protection can be used to override the access protection specified in a TLB entry Fields within the zone protection register ZPR define the protection level of a page or set of pages Mem...

Page 546: ...erPC 401 processors cachelines can be individually locked PowerPC 403 processors not supported PowerPC 405 processors not supported PowerPC 6xx 7xx processors the instruction and data caches can be lo...

Page 547: ...ports two locations for the interrupt handler table 0x000n_nnnn or 0xFFFn_nnnn selected by using the MSR IP bit New exceptions and interrupts are defined Some exceptions and interrupts supported by th...

Page 548: ...798 for a list of implementation dependent PPC405 instructions This table also shows which PPC405 instructions are not supported by the PowerPC architecture Endian Support The default memory access o...

Page 549: ...ment cache management memory synchronization exceptions timer resources and others Many of the differences are reflected the deletion modification and introduction of special purpose registers Porting...

Page 550: ...cache write through register ICCR Instruction cache cacheability register SGR Storage Guarded Register SLER Storage Little Endian Register SU0R Storage User Defined 0 Register ZPR Zone Protection Regi...

Page 551: ...s DECAR Decrementer Auto Reload DNVn1 Data cache normal victim register Cache control DTVn1 Data cache transient victim register DVLIM1 Data cache victim limit INVn1 Instruction cache normal victim re...

Page 552: ...ode is not supported by PowerPC Book E implementations Address translation is always enabled and one or more TLB entries are initialized by the processor during reset so that instructions can be fetch...

Page 553: ...rted by the PowerPC Book E architecture Memory Attributes The PowerPC 40x family and PowerPC Book E processors support the following memory attributes Write through W Caching inhibited I Memory cohere...

Page 554: ...eieio instruction orders all memory accesses This guarantees that existing software that uses eieio works properly in PowerPC Book E implementations The memory synchronize msync instruction replaces...

Page 555: ...registers with the appropriate vector offsets as shown in Table F 7 Some bits in the exception syndrome register ESR are redefined to support different exception conditions These changes are shown in...

Page 556: ...processors can support implementation specific instructions For example the multiply accumulate MAC instructions are considered implementation dependent and are not guaranteed to be supported by othe...

Page 557: ...t See reset clear register instructions 829 compare instructions 398 828 complement register instruction 834 condition register 361 CR mask CRM 423 CR0 361 CR1 362 CR logical instructions 376 828 effe...

Page 558: ...data TLB miss exception 519 data storage exception 507 instruction storage exception 508 machine check exception 504 program exception 512 exception vector prefix register 500 execution model See als...

Page 559: ...chine check enable 504 reset state 562 wait state enable 436 masking interrupts 496 memory coherency 448 memory management 345 memory synchronization See synchronization storage memory control instruc...

Page 560: ...otation 571 SPR See special purpose register SPR general purpose register privileged mode 432 user mode 365 SPRGn See SPR general purpose register SRRn See save restore registers static branch predict...

Page 561: ...torage attribute user defined UISA See PowerPC unconditional UDE See debug events user mode 344 user registers 359 user SPR general purpose register 364 USPRG0 See user SPR general purpose register UT...

Page 562: ...870 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation R...

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